419025b3b4
* kvm-arm64/misc-5.15: : Misc improvements for 5.15: : : - Account the number of VMID-wide TLB invalidations as : remote TLB flushes : - Fix comments in the VGIC code : - Cleanup the PMU IMPDEF identification : - Streamline the TGRAN2 usage : - Avoid advertising a 52bit IPA range for non-64KB configs : - Avoid spurious signalling when a HW-mapped interrupt is in the : A+P state on entry, and in the P state on exit, but that the : physical line is not pending anymore. : - Bunch of minor cleanups KVM: arm64: Trim guest debug exception handling Signed-off-by: Marc Zyngier <maz@kernel.org>
330 lines
8.9 KiB
C
330 lines
8.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2012,2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* Derived from arch/arm/kvm/handle_exit.c:
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University
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* Author: Christoffer Dall <c.dall@virtualopensystems.com>
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*/
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#include <linux/kvm.h>
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#include <linux/kvm_host.h>
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#include <asm/esr.h>
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#include <asm/exception.h>
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#include <asm/kvm_asm.h>
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#include <asm/kvm_emulate.h>
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#include <asm/kvm_mmu.h>
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#include <asm/debug-monitors.h>
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#include <asm/traps.h>
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#include <kvm/arm_hypercalls.h>
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#define CREATE_TRACE_POINTS
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#include "trace_handle_exit.h"
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typedef int (*exit_handle_fn)(struct kvm_vcpu *);
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static void kvm_handle_guest_serror(struct kvm_vcpu *vcpu, u32 esr)
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{
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if (!arm64_is_ras_serror(esr) || arm64_is_fatal_ras_serror(NULL, esr))
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kvm_inject_vabt(vcpu);
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}
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static int handle_hvc(struct kvm_vcpu *vcpu)
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{
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int ret;
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trace_kvm_hvc_arm64(*vcpu_pc(vcpu), vcpu_get_reg(vcpu, 0),
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kvm_vcpu_hvc_get_imm(vcpu));
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vcpu->stat.hvc_exit_stat++;
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ret = kvm_hvc_call_handler(vcpu);
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if (ret < 0) {
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vcpu_set_reg(vcpu, 0, ~0UL);
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return 1;
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}
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return ret;
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}
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static int handle_smc(struct kvm_vcpu *vcpu)
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{
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/*
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* "If an SMC instruction executed at Non-secure EL1 is
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* trapped to EL2 because HCR_EL2.TSC is 1, the exception is a
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* Trap exception, not a Secure Monitor Call exception [...]"
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*
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* We need to advance the PC after the trap, as it would
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* otherwise return to the same address...
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*/
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vcpu_set_reg(vcpu, 0, ~0UL);
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kvm_incr_pc(vcpu);
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return 1;
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}
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/*
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* Guest access to FP/ASIMD registers are routed to this handler only
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* when the system doesn't support FP/ASIMD.
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*/
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static int handle_no_fpsimd(struct kvm_vcpu *vcpu)
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{
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kvm_inject_undefined(vcpu);
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return 1;
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}
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/**
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* kvm_handle_wfx - handle a wait-for-interrupts or wait-for-event
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* instruction executed by a guest
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*
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* @vcpu: the vcpu pointer
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*
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* WFE: Yield the CPU and come back to this vcpu when the scheduler
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* decides to.
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* WFI: Simply call kvm_vcpu_block(), which will halt execution of
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* world-switches and schedule other host processes until there is an
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* incoming IRQ or FIQ to the VM.
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*/
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static int kvm_handle_wfx(struct kvm_vcpu *vcpu)
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{
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if (kvm_vcpu_get_esr(vcpu) & ESR_ELx_WFx_ISS_WFE) {
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trace_kvm_wfx_arm64(*vcpu_pc(vcpu), true);
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vcpu->stat.wfe_exit_stat++;
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kvm_vcpu_on_spin(vcpu, vcpu_mode_priv(vcpu));
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} else {
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trace_kvm_wfx_arm64(*vcpu_pc(vcpu), false);
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vcpu->stat.wfi_exit_stat++;
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kvm_vcpu_block(vcpu);
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kvm_clear_request(KVM_REQ_UNHALT, vcpu);
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}
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kvm_incr_pc(vcpu);
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return 1;
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}
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/**
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* kvm_handle_guest_debug - handle a debug exception instruction
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*
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* @vcpu: the vcpu pointer
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*
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* We route all debug exceptions through the same handler. If both the
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* guest and host are using the same debug facilities it will be up to
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* userspace to re-inject the correct exception for guest delivery.
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*
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* @return: 0 (while setting vcpu->run->exit_reason)
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*/
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static int kvm_handle_guest_debug(struct kvm_vcpu *vcpu)
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{
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struct kvm_run *run = vcpu->run;
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u32 esr = kvm_vcpu_get_esr(vcpu);
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run->exit_reason = KVM_EXIT_DEBUG;
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run->debug.arch.hsr = esr;
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if (ESR_ELx_EC(esr) == ESR_ELx_EC_WATCHPT_LOW)
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run->debug.arch.far = vcpu->arch.fault.far_el2;
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return 0;
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}
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static int kvm_handle_unknown_ec(struct kvm_vcpu *vcpu)
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{
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u32 esr = kvm_vcpu_get_esr(vcpu);
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kvm_pr_unimpl("Unknown exception class: esr: %#08x -- %s\n",
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esr, esr_get_class_string(esr));
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kvm_inject_undefined(vcpu);
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return 1;
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}
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static int handle_sve(struct kvm_vcpu *vcpu)
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{
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/* Until SVE is supported for guests: */
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kvm_inject_undefined(vcpu);
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return 1;
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}
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/*
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* Guest usage of a ptrauth instruction (which the guest EL1 did not turn into
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* a NOP). If we get here, it is that we didn't fixup ptrauth on exit, and all
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* that we can do is give the guest an UNDEF.
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*/
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static int kvm_handle_ptrauth(struct kvm_vcpu *vcpu)
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{
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kvm_inject_undefined(vcpu);
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return 1;
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}
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static exit_handle_fn arm_exit_handlers[] = {
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[0 ... ESR_ELx_EC_MAX] = kvm_handle_unknown_ec,
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[ESR_ELx_EC_WFx] = kvm_handle_wfx,
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[ESR_ELx_EC_CP15_32] = kvm_handle_cp15_32,
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[ESR_ELx_EC_CP15_64] = kvm_handle_cp15_64,
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[ESR_ELx_EC_CP14_MR] = kvm_handle_cp14_32,
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[ESR_ELx_EC_CP14_LS] = kvm_handle_cp14_load_store,
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[ESR_ELx_EC_CP14_64] = kvm_handle_cp14_64,
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[ESR_ELx_EC_HVC32] = handle_hvc,
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[ESR_ELx_EC_SMC32] = handle_smc,
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[ESR_ELx_EC_HVC64] = handle_hvc,
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[ESR_ELx_EC_SMC64] = handle_smc,
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[ESR_ELx_EC_SYS64] = kvm_handle_sys_reg,
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[ESR_ELx_EC_SVE] = handle_sve,
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[ESR_ELx_EC_IABT_LOW] = kvm_handle_guest_abort,
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[ESR_ELx_EC_DABT_LOW] = kvm_handle_guest_abort,
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[ESR_ELx_EC_SOFTSTP_LOW]= kvm_handle_guest_debug,
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[ESR_ELx_EC_WATCHPT_LOW]= kvm_handle_guest_debug,
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[ESR_ELx_EC_BREAKPT_LOW]= kvm_handle_guest_debug,
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[ESR_ELx_EC_BKPT32] = kvm_handle_guest_debug,
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[ESR_ELx_EC_BRK64] = kvm_handle_guest_debug,
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[ESR_ELx_EC_FP_ASIMD] = handle_no_fpsimd,
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[ESR_ELx_EC_PAC] = kvm_handle_ptrauth,
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};
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static exit_handle_fn kvm_get_exit_handler(struct kvm_vcpu *vcpu)
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{
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u32 esr = kvm_vcpu_get_esr(vcpu);
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u8 esr_ec = ESR_ELx_EC(esr);
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return arm_exit_handlers[esr_ec];
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}
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/*
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* We may be single-stepping an emulated instruction. If the emulation
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* has been completed in the kernel, we can return to userspace with a
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* KVM_EXIT_DEBUG, otherwise userspace needs to complete its
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* emulation first.
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*/
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static int handle_trap_exceptions(struct kvm_vcpu *vcpu)
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{
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int handled;
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/*
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* See ARM ARM B1.14.1: "Hyp traps on instructions
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* that fail their condition code check"
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*/
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if (!kvm_condition_valid(vcpu)) {
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kvm_incr_pc(vcpu);
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handled = 1;
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} else {
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exit_handle_fn exit_handler;
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exit_handler = kvm_get_exit_handler(vcpu);
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handled = exit_handler(vcpu);
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}
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return handled;
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}
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/*
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* Return > 0 to return to guest, < 0 on error, 0 (and set exit_reason) on
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* proper exit to userspace.
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*/
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int handle_exit(struct kvm_vcpu *vcpu, int exception_index)
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{
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struct kvm_run *run = vcpu->run;
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exception_index = ARM_EXCEPTION_CODE(exception_index);
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switch (exception_index) {
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case ARM_EXCEPTION_IRQ:
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return 1;
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case ARM_EXCEPTION_EL1_SERROR:
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return 1;
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case ARM_EXCEPTION_TRAP:
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return handle_trap_exceptions(vcpu);
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case ARM_EXCEPTION_HYP_GONE:
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/*
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* EL2 has been reset to the hyp-stub. This happens when a guest
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* is pre-empted by kvm_reboot()'s shutdown call.
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*/
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run->exit_reason = KVM_EXIT_FAIL_ENTRY;
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return 0;
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case ARM_EXCEPTION_IL:
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/*
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* We attempted an illegal exception return. Guest state must
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* have been corrupted somehow. Give up.
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*/
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run->exit_reason = KVM_EXIT_FAIL_ENTRY;
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return -EINVAL;
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default:
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kvm_pr_unimpl("Unsupported exception type: %d",
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exception_index);
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run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
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return 0;
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}
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}
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/* For exit types that need handling before we can be preempted */
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void handle_exit_early(struct kvm_vcpu *vcpu, int exception_index)
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{
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if (ARM_SERROR_PENDING(exception_index)) {
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if (this_cpu_has_cap(ARM64_HAS_RAS_EXTN)) {
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u64 disr = kvm_vcpu_get_disr(vcpu);
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kvm_handle_guest_serror(vcpu, disr_to_esr(disr));
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} else {
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kvm_inject_vabt(vcpu);
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}
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return;
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}
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exception_index = ARM_EXCEPTION_CODE(exception_index);
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if (exception_index == ARM_EXCEPTION_EL1_SERROR)
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kvm_handle_guest_serror(vcpu, kvm_vcpu_get_esr(vcpu));
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}
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void __noreturn __cold nvhe_hyp_panic_handler(u64 esr, u64 spsr,
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u64 elr_virt, u64 elr_phys,
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u64 par, uintptr_t vcpu,
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u64 far, u64 hpfar) {
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u64 elr_in_kimg = __phys_to_kimg(elr_phys);
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u64 hyp_offset = elr_in_kimg - kaslr_offset() - elr_virt;
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u64 mode = spsr & PSR_MODE_MASK;
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/*
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* The nVHE hyp symbols are not included by kallsyms to avoid issues
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* with aliasing. That means that the symbols cannot be printed with the
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* "%pS" format specifier, so fall back to the vmlinux address if
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* there's no better option.
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*/
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if (mode != PSR_MODE_EL2t && mode != PSR_MODE_EL2h) {
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kvm_err("Invalid host exception to nVHE hyp!\n");
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} else if (ESR_ELx_EC(esr) == ESR_ELx_EC_BRK64 &&
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(esr & ESR_ELx_BRK64_ISS_COMMENT_MASK) == BUG_BRK_IMM) {
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const char *file = NULL;
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unsigned int line = 0;
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/* All hyp bugs, including warnings, are treated as fatal. */
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if (!is_protected_kvm_enabled() ||
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IS_ENABLED(CONFIG_NVHE_EL2_DEBUG)) {
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struct bug_entry *bug = find_bug(elr_in_kimg);
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if (bug)
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bug_get_file_line(bug, &file, &line);
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}
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if (file)
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kvm_err("nVHE hyp BUG at: %s:%u!\n", file, line);
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else
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kvm_err("nVHE hyp BUG at: %016llx!\n", elr_virt + hyp_offset);
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} else {
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kvm_err("nVHE hyp panic at: %016llx!\n", elr_virt + hyp_offset);
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}
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/*
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* Hyp has panicked and we're going to handle that by panicking the
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* kernel. The kernel offset will be revealed in the panic so we're
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* also safe to reveal the hyp offset as a debugging aid for translating
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* hyp VAs to vmlinux addresses.
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*/
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kvm_err("Hyp Offset: 0x%llx\n", hyp_offset);
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panic("HYP panic:\nPS:%08llx PC:%016llx ESR:%08llx\nFAR:%016llx HPFAR:%016llx PAR:%016llx\nVCPU:%016lx\n",
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spsr, elr_virt, esr, far, hpfar, par, vcpu);
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}
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