Jisheng Zhang 8237c5243a riscv: Optimize switch_mm by passing "cpu" to flush_icache_deferred() ... Directly passing the cpu to flush_icache_deferred() rather than calling smp_processor_id() again. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> [Palmer: drop the QEMU performance numbers, and update the comment] Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>		2021-05-25 22:50:52 -07:00
..
cacheflush.c	mm: reorder includes after introduction of linux/pgtable.h	2020-06-09 09:39:13 -07:00
context.c	riscv: Optimize switch_mm by passing "cpu" to flush_icache_deferred()	2021-05-25 22:50:52 -07:00
extable.c	riscv: abstract out CSR names for supervisor vs machine mode	2019-11-05 09:20:42 -08:00
fault.c	RISC-V Patches for the 5.13 Merge Window, Part 1	2021-05-06 09:24:18 -07:00
hugetlbpage.c	hugetlbfs: remove hugetlb_add_hstate() warning for existing hstate	2020-06-03 20:09:46 -07:00
init.c	riscv: mm: Drop redundant _sdata and _edata declaration	2021-05-25 22:50:51 -07:00
kasan_init.c	RISC-V Patches for the 5.13 Merge Window, Part 1	2021-05-06 09:24:18 -07:00
Makefile	riscv: Fixup patch_text panic in ftrace	2021-01-14 15:09:04 -08:00
pageattr.c	RISC-V Patches for the 5.11 Merge Window, Part 1	2020-12-18 10:43:07 -08:00
physaddr.c	riscv: Move kernel mapping outside of linear mapping	2021-04-26 08:25:04 -07:00
ptdump.c	riscv: Remove 32b kernel mapping from page table dump	2021-05-01 08:53:32 -07:00
tlbflush.c	riscv: mm: add THP support on 64-bit	2021-05-22 10:20:02 -07:00