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Add Display SubSystem (DSS) DT node for the AM625 SoC. The DSS supports one each of video pipeline (vid) and video-lite pipeline (vidl1). It outputs OLDI signals on one video port (VP1) and DPI signals on another (VP2). The video ports are connected to the pipelines via 2 identical overlay managers (ovr1 and ovr2). Also add the DT node for DSS clock divider. This is a fixed-factor-clock and does not have any register. This comes into effect whenenver OLDI display is used. The input to this divider is a serial clock used by OLDI TXes. The divider divides the input clock by 7, and provides the pixel clock to VP1. Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com> Link: https://lore.kernel.org/r/20230809084559.17322-3-a-bhatia1@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>