db97cc0f74
If the DSP firmware has crashed, some log messages may be pending in the mtrace buffer, but not consumed by the driver as no IPC notification has been sent by the firmware. Check the buffer status for all mtrace slots and ensure any pending log messages are processed before DSP is possibly powered down and the log buffer contents is lost. Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com> Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com> Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com> Link: https://lore.kernel.org/r/20230307110846.2265-1-peter.ujfalusi@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
682 lines
18 KiB
C
682 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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//
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// Copyright(c) 2022 Intel Corporation. All rights reserved.
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#include <linux/debugfs.h>
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#include <linux/sched/signal.h>
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#include <sound/sof/ipc4/header.h>
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#include "sof-priv.h"
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#include "ipc4-priv.h"
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/*
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* debug info window is organized in 16 (equal sized) pages:
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*
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* ------------------------
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* | Page0 - descriptors |
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* ------------------------
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* | Page1 - slot0 |
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* ------------------------
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* | Page2 - slot1 |
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* ------------------------
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* | ... |
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* ------------------------
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* | Page14 - slot13 |
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* ------------------------
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* | Page15 - slot14 |
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* ------------------------
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*
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* The slot size == page size
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*
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* The first page contains descriptors for the remaining 15 cores
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* The slot descriptor is:
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* u32 res_id;
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* u32 type;
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* u32 vma;
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*
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* Log buffer slots have the following layout:
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* u32 host_read_ptr;
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* u32 dsp_write_ptr;
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* u8 buffer[];
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*
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* The two pointers are offsets within the buffer.
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*/
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#define SOF_MTRACE_DESCRIPTOR_SIZE 12 /* 3 x u32 */
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#define FW_EPOCH_DELTA 11644473600LL
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#define INVALID_SLOT_OFFSET 0xffffffff
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#define MAX_ALLOWED_LIBRARIES 16
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#define MAX_MTRACE_SLOTS 15
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#define SOF_MTRACE_PAGE_SIZE 0x1000
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#define SOF_MTRACE_SLOT_SIZE SOF_MTRACE_PAGE_SIZE
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/* debug log slot types */
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#define SOF_MTRACE_SLOT_UNUSED 0x00000000
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#define SOF_MTRACE_SLOT_CRITICAL_LOG 0x54524300 /* byte 0: core ID */
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#define SOF_MTRACE_SLOT_DEBUG_LOG 0x474f4c00 /* byte 0: core ID */
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#define SOF_MTRACE_SLOT_GDB_STUB 0x42444700
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#define SOF_MTRACE_SLOT_TELEMETRY 0x4c455400
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#define SOF_MTRACE_SLOT_BROKEN 0x44414544
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/* for debug and critical types */
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#define SOF_MTRACE_SLOT_CORE_MASK GENMASK(7, 0)
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#define SOF_MTRACE_SLOT_TYPE_MASK GENMASK(31, 8)
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#define DEFAULT_AGING_TIMER_PERIOD_MS 0x100
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#define DEFAULT_FIFO_FULL_TIMER_PERIOD_MS 0x1000
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/* ipc4 log level and source definitions for logs_priorities_mask */
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#define SOF_MTRACE_LOG_LEVEL_CRITICAL BIT(0)
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#define SOF_MTRACE_LOG_LEVEL_ERROR BIT(1)
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#define SOF_MTRACE_LOG_LEVEL_WARNING BIT(2)
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#define SOF_MTRACE_LOG_LEVEL_INFO BIT(3)
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#define SOF_MTRACE_LOG_LEVEL_VERBOSE BIT(4)
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#define SOF_MTRACE_LOG_SOURCE_INFRA BIT(5) /* log source 0 */
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#define SOF_MTRACE_LOG_SOURCE_HAL BIT(6)
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#define SOF_MTRACE_LOG_SOURCE_MODULE BIT(7)
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#define SOF_MTRACE_LOG_SOURCE_AUDIO BIT(8)
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#define SOF_MTRACE_LOG_SOURCE_SCHEDULER BIT(9)
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#define SOF_MTRACE_LOG_SOURCE_ULP_INFRA BIT(10)
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#define SOF_MTRACE_LOG_SOURCE_ULP_MODULE BIT(11)
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#define SOF_MTRACE_LOG_SOURCE_VISION BIT(12) /* log source 7 */
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#define DEFAULT_LOGS_PRIORITIES_MASK (SOF_MTRACE_LOG_LEVEL_CRITICAL | \
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SOF_MTRACE_LOG_LEVEL_ERROR | \
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SOF_MTRACE_LOG_LEVEL_WARNING | \
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SOF_MTRACE_LOG_LEVEL_INFO | \
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SOF_MTRACE_LOG_SOURCE_INFRA | \
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SOF_MTRACE_LOG_SOURCE_HAL | \
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SOF_MTRACE_LOG_SOURCE_MODULE | \
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SOF_MTRACE_LOG_SOURCE_AUDIO)
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struct sof_log_state_info {
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u32 aging_timer_period;
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u32 fifo_full_timer_period;
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u32 enable;
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u32 logs_priorities_mask[MAX_ALLOWED_LIBRARIES];
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} __packed;
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enum sof_mtrace_state {
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SOF_MTRACE_DISABLED,
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SOF_MTRACE_INITIALIZING,
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SOF_MTRACE_ENABLED,
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};
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struct sof_mtrace_core_data {
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struct snd_sof_dev *sdev;
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int id;
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u32 slot_offset;
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void *log_buffer;
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struct mutex buffer_lock; /* for log_buffer alloc/free */
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u32 host_read_ptr;
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u32 dsp_write_ptr;
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/* pos update IPC arrived before the slot offset is known, queried */
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bool delayed_pos_update;
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wait_queue_head_t trace_sleep;
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};
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struct sof_mtrace_priv {
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struct snd_sof_dev *sdev;
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enum sof_mtrace_state mtrace_state;
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struct sof_log_state_info state_info;
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struct sof_mtrace_core_data cores[];
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};
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static int sof_ipc4_mtrace_dfs_open(struct inode *inode, struct file *file)
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{
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struct sof_mtrace_core_data *core_data = inode->i_private;
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int ret;
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mutex_lock(&core_data->buffer_lock);
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if (core_data->log_buffer) {
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ret = -EBUSY;
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goto out;
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}
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ret = debugfs_file_get(file->f_path.dentry);
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if (unlikely(ret))
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goto out;
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core_data->log_buffer = kmalloc(SOF_MTRACE_SLOT_SIZE, GFP_KERNEL);
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if (!core_data->log_buffer) {
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debugfs_file_put(file->f_path.dentry);
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ret = -ENOMEM;
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goto out;
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}
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ret = simple_open(inode, file);
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if (ret) {
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kfree(core_data->log_buffer);
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debugfs_file_put(file->f_path.dentry);
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}
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out:
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mutex_unlock(&core_data->buffer_lock);
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return ret;
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}
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static bool sof_wait_mtrace_avail(struct sof_mtrace_core_data *core_data)
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{
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wait_queue_entry_t wait;
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/* data immediately available */
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if (core_data->host_read_ptr != core_data->dsp_write_ptr)
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return true;
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/* wait for available trace data from FW */
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init_waitqueue_entry(&wait, current);
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set_current_state(TASK_INTERRUPTIBLE);
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add_wait_queue(&core_data->trace_sleep, &wait);
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if (!signal_pending(current)) {
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/* set timeout to max value, no error code */
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schedule_timeout(MAX_SCHEDULE_TIMEOUT);
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}
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remove_wait_queue(&core_data->trace_sleep, &wait);
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if (core_data->host_read_ptr != core_data->dsp_write_ptr)
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return true;
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return false;
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}
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static ssize_t sof_ipc4_mtrace_dfs_read(struct file *file, char __user *buffer,
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size_t count, loff_t *ppos)
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{
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struct sof_mtrace_core_data *core_data = file->private_data;
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u32 log_buffer_offset, log_buffer_size, read_ptr, write_ptr;
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struct snd_sof_dev *sdev = core_data->sdev;
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struct sof_mtrace_priv *priv = sdev->fw_trace_data;
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void *log_buffer = core_data->log_buffer;
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loff_t lpos = *ppos;
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u32 avail;
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int ret;
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/* check pos and count */
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if (lpos < 0)
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return -EINVAL;
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if (!count || count < sizeof(avail))
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return 0;
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/* get available count based on current host offset */
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if (!sof_wait_mtrace_avail(core_data)) {
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/* No data available */
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avail = 0;
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if (copy_to_user(buffer, &avail, sizeof(avail)))
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return -EFAULT;
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return 0;
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}
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if (core_data->slot_offset == INVALID_SLOT_OFFSET)
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return 0;
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/* The log data buffer starts after the two pointer in the slot */
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log_buffer_offset = core_data->slot_offset + (sizeof(u32) * 2);
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/* The log data size excludes the pointers */
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log_buffer_size = SOF_MTRACE_SLOT_SIZE - (sizeof(u32) * 2);
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read_ptr = core_data->host_read_ptr;
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write_ptr = core_data->dsp_write_ptr;
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if (read_ptr < write_ptr)
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avail = write_ptr - read_ptr;
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else
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avail = log_buffer_size - read_ptr + write_ptr;
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if (!avail)
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return 0;
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if (avail > log_buffer_size)
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avail = log_buffer_size;
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/* Need space for the initial u32 of the avail */
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if (avail > count - sizeof(avail))
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avail = count - sizeof(avail);
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if (sof_debug_check_flag(SOF_DBG_PRINT_DMA_POSITION_UPDATE_LOGS))
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dev_dbg(sdev->dev,
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"core%d, host read: %#x, dsp write: %#x, avail: %#x\n",
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core_data->id, read_ptr, write_ptr, avail);
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if (read_ptr < write_ptr) {
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/* Read data between read pointer and write pointer */
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sof_mailbox_read(sdev, log_buffer_offset + read_ptr, log_buffer, avail);
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} else {
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/* read from read pointer to end of the slot */
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sof_mailbox_read(sdev, log_buffer_offset + read_ptr, log_buffer,
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avail - write_ptr);
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/* read from slot start to write pointer */
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if (write_ptr)
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sof_mailbox_read(sdev, log_buffer_offset,
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(u8 *)(log_buffer) + avail - write_ptr,
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write_ptr);
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}
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/* first write the number of bytes we have gathered */
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ret = copy_to_user(buffer, &avail, sizeof(avail));
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if (ret)
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return -EFAULT;
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/* Followed by the data itself */
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ret = copy_to_user(buffer + sizeof(avail), log_buffer, avail);
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if (ret)
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return -EFAULT;
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/* Update the host_read_ptr in the slot for this core */
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read_ptr += avail;
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if (read_ptr >= log_buffer_size)
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read_ptr -= log_buffer_size;
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sof_mailbox_write(sdev, core_data->slot_offset, &read_ptr, sizeof(read_ptr));
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/* Only update the host_read_ptr if mtrace is enabled */
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if (priv->mtrace_state != SOF_MTRACE_DISABLED)
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core_data->host_read_ptr = read_ptr;
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/*
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* Ask for a new buffer from user space for the next chunk, not
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* streaming due to the heading number of bytes value.
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*/
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*ppos += count;
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return count;
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}
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static int sof_ipc4_mtrace_dfs_release(struct inode *inode, struct file *file)
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{
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struct sof_mtrace_core_data *core_data = inode->i_private;
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debugfs_file_put(file->f_path.dentry);
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mutex_lock(&core_data->buffer_lock);
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kfree(core_data->log_buffer);
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core_data->log_buffer = NULL;
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mutex_unlock(&core_data->buffer_lock);
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return 0;
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}
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static const struct file_operations sof_dfs_mtrace_fops = {
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.open = sof_ipc4_mtrace_dfs_open,
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.read = sof_ipc4_mtrace_dfs_read,
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.llseek = default_llseek,
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.release = sof_ipc4_mtrace_dfs_release,
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.owner = THIS_MODULE,
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};
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static ssize_t sof_ipc4_priority_mask_dfs_read(struct file *file, char __user *to,
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size_t count, loff_t *ppos)
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{
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struct sof_mtrace_priv *priv = file->private_data;
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int i, ret, offset, remaining;
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char *buf;
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/*
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* one entry (14 char + new line = 15):
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* " 0: 000001ef"
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*
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* 16 * 15 + 1 = 241
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*/
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buf = kzalloc(241, GFP_KERNEL);
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if (!buf)
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return -ENOMEM;
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for (i = 0; i < MAX_ALLOWED_LIBRARIES; i++) {
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offset = strlen(buf);
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remaining = 241 - offset;
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snprintf(buf + offset, remaining, "%2d: 0x%08x\n", i,
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priv->state_info.logs_priorities_mask[i]);
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}
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ret = simple_read_from_buffer(to, count, ppos, buf, strlen(buf));
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kfree(buf);
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return ret;
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}
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static ssize_t sof_ipc4_priority_mask_dfs_write(struct file *file,
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const char __user *from,
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size_t count, loff_t *ppos)
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{
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struct sof_mtrace_priv *priv = file->private_data;
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unsigned int id;
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char *buf;
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u32 mask;
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int ret;
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/*
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* To update Nth mask entry, write:
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* "N,0x1234" or "N,1234" to the debugfs file
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* The mask will be interpreted as hexadecimal number
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*/
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buf = memdup_user_nul(from, count);
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if (IS_ERR(buf))
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return PTR_ERR(buf);
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ret = sscanf(buf, "%u,0x%x", &id, &mask);
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if (ret != 2) {
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ret = sscanf(buf, "%u,%x", &id, &mask);
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if (ret != 2) {
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ret = -EINVAL;
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goto out;
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}
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}
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if (id >= MAX_ALLOWED_LIBRARIES) {
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ret = -EINVAL;
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goto out;
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}
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priv->state_info.logs_priorities_mask[id] = mask;
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ret = count;
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out:
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kfree(buf);
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return ret;
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}
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static const struct file_operations sof_dfs_priority_mask_fops = {
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.open = simple_open,
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.read = sof_ipc4_priority_mask_dfs_read,
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.write = sof_ipc4_priority_mask_dfs_write,
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.llseek = default_llseek,
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.owner = THIS_MODULE,
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};
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static int mtrace_debugfs_create(struct snd_sof_dev *sdev)
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{
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struct sof_mtrace_priv *priv = sdev->fw_trace_data;
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struct dentry *dfs_root;
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char dfs_name[100];
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int i;
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dfs_root = debugfs_create_dir("mtrace", sdev->debugfs_root);
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if (IS_ERR_OR_NULL(dfs_root))
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return 0;
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/* Create files for the logging parameters */
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debugfs_create_u32("aging_timer_period", 0644, dfs_root,
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&priv->state_info.aging_timer_period);
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debugfs_create_u32("fifo_full_timer_period", 0644, dfs_root,
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&priv->state_info.fifo_full_timer_period);
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debugfs_create_file("logs_priorities_mask", 0644, dfs_root, priv,
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&sof_dfs_priority_mask_fops);
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/* Separate log files per core */
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for (i = 0; i < sdev->num_cores; i++) {
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snprintf(dfs_name, sizeof(dfs_name), "core%d", i);
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debugfs_create_file(dfs_name, 0444, dfs_root, &priv->cores[i],
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&sof_dfs_mtrace_fops);
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}
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return 0;
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}
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static int ipc4_mtrace_enable(struct snd_sof_dev *sdev)
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{
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struct sof_mtrace_priv *priv = sdev->fw_trace_data;
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const struct sof_ipc_ops *iops = sdev->ipc->ops;
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struct sof_ipc4_msg msg;
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u64 system_time;
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ktime_t kt;
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int ret;
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if (priv->mtrace_state != SOF_MTRACE_DISABLED)
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return 0;
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msg.primary = SOF_IPC4_MSG_TARGET(SOF_IPC4_MODULE_MSG);
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msg.primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
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msg.primary |= SOF_IPC4_MOD_ID(SOF_IPC4_MOD_INIT_BASEFW_MOD_ID);
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msg.primary |= SOF_IPC4_MOD_INSTANCE(SOF_IPC4_MOD_INIT_BASEFW_INSTANCE_ID);
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msg.extension = SOF_IPC4_MOD_EXT_MSG_PARAM_ID(SOF_IPC4_FW_PARAM_SYSTEM_TIME);
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/* The system time is in usec, UTC, epoch is 1601-01-01 00:00:00 */
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kt = ktime_add_us(ktime_get_real(), FW_EPOCH_DELTA * USEC_PER_SEC);
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system_time = ktime_to_us(kt);
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msg.data_size = sizeof(system_time);
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msg.data_ptr = &system_time;
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ret = iops->set_get_data(sdev, &msg, msg.data_size, true);
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if (ret)
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return ret;
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msg.extension = SOF_IPC4_MOD_EXT_MSG_PARAM_ID(SOF_IPC4_FW_PARAM_ENABLE_LOGS);
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priv->state_info.enable = 1;
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msg.data_size = sizeof(priv->state_info);
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msg.data_ptr = &priv->state_info;
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priv->mtrace_state = SOF_MTRACE_INITIALIZING;
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ret = iops->set_get_data(sdev, &msg, msg.data_size, true);
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if (ret) {
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priv->mtrace_state = SOF_MTRACE_DISABLED;
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return ret;
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}
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priv->mtrace_state = SOF_MTRACE_ENABLED;
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return 0;
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}
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static void ipc4_mtrace_disable(struct snd_sof_dev *sdev)
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{
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struct sof_mtrace_priv *priv = sdev->fw_trace_data;
|
|
const struct sof_ipc_ops *iops = sdev->ipc->ops;
|
|
struct sof_ipc4_msg msg;
|
|
int i;
|
|
|
|
if (priv->mtrace_state == SOF_MTRACE_DISABLED)
|
|
return;
|
|
|
|
msg.primary = SOF_IPC4_MSG_TARGET(SOF_IPC4_MODULE_MSG);
|
|
msg.primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
|
|
msg.primary |= SOF_IPC4_MOD_ID(SOF_IPC4_MOD_INIT_BASEFW_MOD_ID);
|
|
msg.primary |= SOF_IPC4_MOD_INSTANCE(SOF_IPC4_MOD_INIT_BASEFW_INSTANCE_ID);
|
|
msg.extension = SOF_IPC4_MOD_EXT_MSG_PARAM_ID(SOF_IPC4_FW_PARAM_ENABLE_LOGS);
|
|
|
|
priv->state_info.enable = 0;
|
|
|
|
msg.data_size = sizeof(priv->state_info);
|
|
msg.data_ptr = &priv->state_info;
|
|
iops->set_get_data(sdev, &msg, msg.data_size, true);
|
|
|
|
priv->mtrace_state = SOF_MTRACE_DISABLED;
|
|
|
|
for (i = 0; i < sdev->num_cores; i++) {
|
|
struct sof_mtrace_core_data *core_data = &priv->cores[i];
|
|
|
|
core_data->host_read_ptr = 0;
|
|
core_data->dsp_write_ptr = 0;
|
|
wake_up(&core_data->trace_sleep);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Each DSP core logs to a dedicated slot.
|
|
* Parse the slot descriptors at debug_box offset to find the debug log slots
|
|
* and map them to cores.
|
|
* There are 15 slots and therefore 15 descriptors to check (MAX_MTRACE_SLOTS)
|
|
*/
|
|
static void sof_mtrace_find_core_slots(struct snd_sof_dev *sdev)
|
|
{
|
|
struct sof_mtrace_priv *priv = sdev->fw_trace_data;
|
|
struct sof_mtrace_core_data *core_data;
|
|
u32 slot_desc_type_offset, type, core;
|
|
int i;
|
|
|
|
for (i = 0; i < MAX_MTRACE_SLOTS; i++) {
|
|
/* The type is the second u32 in the slot descriptor */
|
|
slot_desc_type_offset = sdev->debug_box.offset;
|
|
slot_desc_type_offset += SOF_MTRACE_DESCRIPTOR_SIZE * i + sizeof(u32);
|
|
sof_mailbox_read(sdev, slot_desc_type_offset, &type, sizeof(type));
|
|
|
|
if ((type & SOF_MTRACE_SLOT_TYPE_MASK) == SOF_MTRACE_SLOT_DEBUG_LOG) {
|
|
core = type & SOF_MTRACE_SLOT_CORE_MASK;
|
|
|
|
if (core >= sdev->num_cores) {
|
|
dev_dbg(sdev->dev, "core%u is invalid for slot%d\n",
|
|
core, i);
|
|
continue;
|
|
}
|
|
|
|
core_data = &priv->cores[core];
|
|
/*
|
|
* The area reserved for descriptors have the same size
|
|
* as a slot.
|
|
* In other words: slot0 starts at
|
|
* debug_box + SOF_MTRACE_SLOT_SIZE offset
|
|
*/
|
|
core_data->slot_offset = sdev->debug_box.offset;
|
|
core_data->slot_offset += SOF_MTRACE_SLOT_SIZE * (i + 1);
|
|
dev_dbg(sdev->dev, "slot%d is used for core%u\n", i, core);
|
|
if (core_data->delayed_pos_update) {
|
|
sof_ipc4_mtrace_update_pos(sdev, core);
|
|
core_data->delayed_pos_update = false;
|
|
}
|
|
} else if (type) {
|
|
dev_dbg(sdev->dev, "slot%d is not a log slot (%#x)\n", i, type);
|
|
}
|
|
}
|
|
}
|
|
|
|
static int ipc4_mtrace_init(struct snd_sof_dev *sdev)
|
|
{
|
|
struct sof_ipc4_fw_data *ipc4_data = sdev->private;
|
|
struct sof_mtrace_priv *priv;
|
|
int i, ret;
|
|
|
|
if (sdev->fw_trace_data) {
|
|
dev_err(sdev->dev, "fw_trace_data has been already allocated\n");
|
|
return -EBUSY;
|
|
}
|
|
|
|
if (!ipc4_data->mtrace_log_bytes ||
|
|
ipc4_data->mtrace_type != SOF_IPC4_MTRACE_INTEL_CAVS_2) {
|
|
sdev->fw_trace_is_supported = false;
|
|
return 0;
|
|
}
|
|
|
|
priv = devm_kzalloc(sdev->dev, struct_size(priv, cores, sdev->num_cores),
|
|
GFP_KERNEL);
|
|
if (!priv)
|
|
return -ENOMEM;
|
|
|
|
sdev->fw_trace_data = priv;
|
|
|
|
/* Set initial values for mtrace parameters */
|
|
priv->state_info.aging_timer_period = DEFAULT_AGING_TIMER_PERIOD_MS;
|
|
priv->state_info.fifo_full_timer_period = DEFAULT_FIFO_FULL_TIMER_PERIOD_MS;
|
|
/* Only enable basefw logs initially (index 0 is always basefw) */
|
|
priv->state_info.logs_priorities_mask[0] = DEFAULT_LOGS_PRIORITIES_MASK;
|
|
|
|
for (i = 0; i < sdev->num_cores; i++) {
|
|
struct sof_mtrace_core_data *core_data = &priv->cores[i];
|
|
|
|
init_waitqueue_head(&core_data->trace_sleep);
|
|
mutex_init(&core_data->buffer_lock);
|
|
core_data->sdev = sdev;
|
|
core_data->id = i;
|
|
}
|
|
|
|
ret = ipc4_mtrace_enable(sdev);
|
|
if (ret) {
|
|
/*
|
|
* Mark firmware tracing as not supported and return 0 to not
|
|
* block the whole audio stack
|
|
*/
|
|
sdev->fw_trace_is_supported = false;
|
|
dev_dbg(sdev->dev, "initialization failed, fw tracing is disabled\n");
|
|
return 0;
|
|
}
|
|
|
|
sof_mtrace_find_core_slots(sdev);
|
|
|
|
ret = mtrace_debugfs_create(sdev);
|
|
if (ret)
|
|
ipc4_mtrace_disable(sdev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void ipc4_mtrace_free(struct snd_sof_dev *sdev)
|
|
{
|
|
ipc4_mtrace_disable(sdev);
|
|
}
|
|
|
|
static int sof_ipc4_mtrace_update_pos_all_cores(struct snd_sof_dev *sdev)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < sdev->num_cores; i++)
|
|
sof_ipc4_mtrace_update_pos(sdev, i);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int sof_ipc4_mtrace_update_pos(struct snd_sof_dev *sdev, int core)
|
|
{
|
|
struct sof_mtrace_priv *priv = sdev->fw_trace_data;
|
|
struct sof_mtrace_core_data *core_data;
|
|
|
|
if (!sdev->fw_trace_is_supported ||
|
|
priv->mtrace_state == SOF_MTRACE_DISABLED)
|
|
return 0;
|
|
|
|
if (core >= sdev->num_cores)
|
|
return -EINVAL;
|
|
|
|
core_data = &priv->cores[core];
|
|
|
|
if (core_data->slot_offset == INVALID_SLOT_OFFSET) {
|
|
core_data->delayed_pos_update = true;
|
|
return 0;
|
|
}
|
|
|
|
/* Read out the dsp_write_ptr from the slot for this core */
|
|
sof_mailbox_read(sdev, core_data->slot_offset + sizeof(u32),
|
|
&core_data->dsp_write_ptr, 4);
|
|
core_data->dsp_write_ptr -= core_data->dsp_write_ptr % 4;
|
|
|
|
if (sof_debug_check_flag(SOF_DBG_PRINT_DMA_POSITION_UPDATE_LOGS))
|
|
dev_dbg(sdev->dev, "core%d, host read: %#x, dsp write: %#x",
|
|
core, core_data->host_read_ptr, core_data->dsp_write_ptr);
|
|
|
|
wake_up(&core_data->trace_sleep);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void ipc4_mtrace_fw_crashed(struct snd_sof_dev *sdev)
|
|
{
|
|
/*
|
|
* The DSP might not be able to send SOF_IPC4_NOTIFY_LOG_BUFFER_STATUS
|
|
* messages anymore, so check the log buffer status on all
|
|
* cores and process any pending messages.
|
|
*/
|
|
sof_ipc4_mtrace_update_pos_all_cores(sdev);
|
|
}
|
|
|
|
static int ipc4_mtrace_resume(struct snd_sof_dev *sdev)
|
|
{
|
|
return ipc4_mtrace_enable(sdev);
|
|
}
|
|
|
|
static void ipc4_mtrace_suspend(struct snd_sof_dev *sdev, pm_message_t pm_state)
|
|
{
|
|
ipc4_mtrace_disable(sdev);
|
|
}
|
|
|
|
const struct sof_ipc_fw_tracing_ops ipc4_mtrace_ops = {
|
|
.init = ipc4_mtrace_init,
|
|
.free = ipc4_mtrace_free,
|
|
.fw_crashed = ipc4_mtrace_fw_crashed,
|
|
.suspend = ipc4_mtrace_suspend,
|
|
.resume = ipc4_mtrace_resume,
|
|
};
|