8e27a2d4cd
[Why] If voltage level > 0, DCFCLK and SOCCLK could be 0 during DML calculations, which ended up causing an assert. [How] Initialize dcfclk_mhz and socclk_mhz values according to the voltage level. Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>