8e312baacc
Add dt-binding documentation for Versal NET platforms. Versal Net is a new AMD/Xilinx SoC. The SoC and its architecture is based on the Versal ACAP device. The Versal Net device includes more security features in the platform management controller (PMC) and increases the number of CPUs in the application processing unit (APU) and the real-time processing unit (RPU). Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@xilinx.com> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/1705406326-2947516-1-git-send-email-radhey.shyam.pandey@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
110 lines
3.0 KiB
YAML
110 lines
3.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Xilinx firmware driver
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maintainers:
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- Nava kishore Manne <nava.kishore.manne@amd.com>
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description: The zynqmp-firmware node describes the interface to platform
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firmware. ZynqMP has an interface to communicate with secure firmware.
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Firmware driver provides an interface to firmware APIs. Interface APIs
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can be used by any driver to communicate to PMUFW(Platform Management Unit).
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These requests include clock management, pin control, device control,
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power management service, FPGA service and other platform management
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services.
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properties:
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compatible:
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oneOf:
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- description: For implementations complying for Zynq Ultrascale+ MPSoC.
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const: xlnx,zynqmp-firmware
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- description: For implementations complying for Versal.
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const: xlnx,versal-firmware
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- description: For implementations complying for Versal NET.
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items:
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- enum:
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- xlnx,versal-net-firmware
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- const: xlnx,versal-firmware
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method:
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description: |
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The method of calling the PM-API firmware layer.
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Permitted values are.
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- "smc" : SMC #0, following the SMCCC
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- "hvc" : HVC #0, following the SMCCC
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$ref: /schemas/types.yaml#/definitions/string-array
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enum:
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- smc
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- hvc
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"#power-domain-cells":
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const: 1
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versal_fpga:
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$ref: /schemas/fpga/xlnx,versal-fpga.yaml#
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description: Compatible of the FPGA device.
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type: object
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zynqmp-aes:
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$ref: /schemas/crypto/xlnx,zynqmp-aes.yaml#
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description: The ZynqMP AES-GCM hardened cryptographic accelerator is
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used to encrypt or decrypt the data with provided key and initialization
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vector.
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type: object
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clock-controller:
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$ref: /schemas/clock/xlnx,versal-clk.yaml#
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description: The clock controller is a hardware block of Xilinx versal
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clock tree. It reads required input clock frequencies from the devicetree
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and acts as clock provider for all clock consumers of PS clocks.list of
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clock specifiers which are external input clocks to the given clock
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controller.
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type: object
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required:
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- compatible
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/power/xlnx-zynqmp-power.h>
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firmware {
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zynqmp_firmware: zynqmp-firmware {
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#power-domain-cells = <1>;
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};
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};
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sata {
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power-domains = <&zynqmp_firmware PD_SATA>;
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};
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versal-firmware {
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compatible = "xlnx,versal-firmware";
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method = "smc";
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versal_fpga: versal_fpga {
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compatible = "xlnx,versal-fpga";
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};
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xlnx_aes: zynqmp-aes {
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compatible = "xlnx,zynqmp-aes";
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};
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versal_clk: clock-controller {
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#clock-cells = <1>;
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compatible = "xlnx,versal-clk";
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clocks = <&ref>, <&pl_alt_ref>;
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clock-names = "ref", "pl_alt_ref";
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};
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};
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...
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