linux

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Linus Torvalds 22b2e2d6ab RISC-V Fixes for 6.0-rc5

* A pair of device tree fixes for the Polarfire SOC.
 * A fix to avoid overflowing the PMU counter array when firmware
   incorrectly reports the number of supported counters, which manifests
   on OpenSBI versions prior to 1.1.
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Merge tag 'riscv-for-linus-6.0-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V fixes from Palmer Dabbelt:

 - A pair of device tree fixes for the Polarfire SOC

 - A fix to avoid overflowing the PMU counter array when firmware
   incorrectly reports the number of supported counters, which manifests
   on OpenSBI versions prior to 1.1

* tag 'riscv-for-linus-6.0-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  perf: RISC-V: fix access beyond allocated array
  riscv: dts: microchip: use an mpfs specific l2 compatible
  dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible

2022-09-09 14:06:10 -04:00

boot

riscv: dts: microchip: use an mpfs specific l2 compatible

2022-08-31 16:57:51 +01:00

configs

riscv: enable Docker requirements in defconfig

2022-07-22 13:43:28 -07:00

errata

riscv: implement Zicbom-based CMO instructions + the t-head variant

2022-08-10 20:49:32 -07:00

include

PCI interpretation compile fixes