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Kan Liang 8f5d41f3a0 perf/x86/intel/uncore: Update Ice Lake uncore units

There are some updates for the Icelake model specific uncore performance
monitors. (The update can be found at 10th generation intel core
processors families specification update Revision 004, ICL068)

1) Counter 0 of ARB uncore unit is not available for software use
2) The global 'enable bit' (bit 29) and 'freeze bit' (bit 31) of
   MSR_UNC_PERF_GLOBAL_CTRL cannot be used to control counter behavior.
   Needs to use local enable in event select MSR.

Accessing the modified bit/registers will be ignored by HW. Users may
observe inaccurate results with the current code.

The changes of the MSR_UNC_PERF_GLOBAL_CTRL imply that groups cannot be
read atomically anymore. Although the error of the result for a group
becomes a bit bigger, it still far lower than not using a group. The
group support is still kept. Only Remove the *_box() related
implementation.

Since the counter 0 of ARB uncore unit is not available, update the MSR
address for the ARB uncore unit.

There is no change for IMC uncore unit, which only include free-running
counters.

Fixes: 6e394376ee89 ("perf/x86/intel/uncore: Add Intel Icelake uncore support")
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20200925134905.8839-2-kan.liang@linux.intel.com

2020-09-29 09:57:01 +02:00

bts.c

perf/x86: Replace zero-length array with flexible-array

2020-05-19 20:34:16 +02:00

core.c

perf/x86/intel: Support per-thread RDPMC TopDown metrics

2020-08-18 16:34:37 +02:00

cstate.c

perf/x86/cstate: Add Jasper Lake CPU support

2020-04-22 21:43:12 +02:00

ds.c

perf/x86/intel/ds: Fix x86_pmu_stop warning for large PEBS