Conor Dooley 9009f55bc4 riscv: config: enable SOC_STARFIVE in defconfig ... SOC_STARFIVE is the odd one out among the (compatible) SOC_FOO options as it is not enabled in the default defconfig. Add it to make catching dt regressions etc easier. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Emil Renner Berthing <kernel@esmil.dk> Link: https://lore.kernel.org/r/20220617182424.324276-1-mail@conchuod.ie Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>		2022-07-14 11:06:59 -07:00
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32-bit.config	riscv: add rv32 and rv64 randconfig build targets	2021-10-04 17:46:02 -07:00
64-bit.config	riscv: add rv32 and rv64 randconfig build targets	2021-10-04 17:46:02 -07:00
defconfig	riscv: config: enable SOC_STARFIVE in defconfig	2022-07-14 11:06:59 -07:00
nommu_k210_defconfig	RISC-V: K210 defconfigs: Drop redundant MEMBARRIER=n	2022-03-31 17:19:27 -07:00
nommu_k210_sdcard_defconfig	RISC-V: K210 defconfigs: Drop redundant MEMBARRIER=n	2022-03-31 17:19:27 -07:00
nommu_virt_defconfig	RISC-V: K210 defconfigs: Drop redundant MEMBARRIER=n	2022-03-31 17:19:27 -07:00
rv32_defconfig	RISC-V: configs: Configs that had RPMSG_CHAR now get RPMSG_CTRL	2022-04-26 08:19:53 -07:00