a4b16dad46
With the growing number of Intel crypto drivers, it makes sense to group them all into a single drivers/crypto/intel/ directory. Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
45 lines
1.4 KiB
C
45 lines
1.4 KiB
C
/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
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/* Copyright(c) 2022 Intel Corporation */
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#ifndef ADF_GEN4_PM_H
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#define ADF_GEN4_PM_H
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#include "adf_accel_devices.h"
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/* Power management registers */
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#define ADF_GEN4_PM_HOST_MSG (0x50A01C)
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/* Power management */
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#define ADF_GEN4_PM_POLL_DELAY_US 20
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#define ADF_GEN4_PM_POLL_TIMEOUT_US USEC_PER_SEC
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#define ADF_GEN4_PM_MSG_POLL_DELAY_US (10 * USEC_PER_MSEC)
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#define ADF_GEN4_PM_STATUS (0x50A00C)
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#define ADF_GEN4_PM_INTERRUPT (0x50A028)
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/* Power management source in ERRSOU2 and ERRMSK2 */
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#define ADF_GEN4_PM_SOU BIT(18)
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#define ADF_GEN4_PM_IDLE_INT_EN BIT(18)
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#define ADF_GEN4_PM_THROTTLE_INT_EN BIT(19)
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#define ADF_GEN4_PM_DRV_ACTIVE BIT(20)
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#define ADF_GEN4_PM_INIT_STATE BIT(21)
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#define ADF_GEN4_PM_INT_EN_DEFAULT (ADF_GEN4_PM_IDLE_INT_EN | \
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ADF_GEN4_PM_THROTTLE_INT_EN)
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#define ADF_GEN4_PM_THR_STS BIT(0)
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#define ADF_GEN4_PM_IDLE_STS BIT(1)
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#define ADF_GEN4_PM_FW_INT_STS BIT(2)
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#define ADF_GEN4_PM_INT_STS_MASK (ADF_GEN4_PM_THR_STS | \
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ADF_GEN4_PM_IDLE_STS | \
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ADF_GEN4_PM_FW_INT_STS)
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#define ADF_GEN4_PM_MSG_PENDING BIT(0)
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#define ADF_GEN4_PM_MSG_PAYLOAD_BIT_MASK GENMASK(28, 1)
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#define ADF_GEN4_PM_DEFAULT_IDLE_FILTER (0x0)
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#define ADF_GEN4_PM_MAX_IDLE_FILTER (0x7)
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int adf_gen4_enable_pm(struct adf_accel_dev *accel_dev);
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bool adf_gen4_handle_pm_interrupt(struct adf_accel_dev *accel_dev);
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#endif
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