837d542a09
Instead of centralizing all headers in the same folder. Separate them into different folders and place them among those source files those who really need them. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
432 lines
14 KiB
C
432 lines
14 KiB
C
/*
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* Copyright 2013 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef PP_SISLANDS_SMC_H
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#define PP_SISLANDS_SMC_H
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#include "ppsmc.h"
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#pragma pack(push, 1)
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#define SISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 16
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struct PP_SIslands_Dpm2PerfLevel
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{
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uint8_t MaxPS;
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uint8_t TgtAct;
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uint8_t MaxPS_StepInc;
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uint8_t MaxPS_StepDec;
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uint8_t PSSamplingTime;
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uint8_t NearTDPDec;
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uint8_t AboveSafeInc;
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uint8_t BelowSafeInc;
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uint8_t PSDeltaLimit;
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uint8_t PSDeltaWin;
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uint16_t PwrEfficiencyRatio;
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uint8_t Reserved[4];
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};
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typedef struct PP_SIslands_Dpm2PerfLevel PP_SIslands_Dpm2PerfLevel;
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struct PP_SIslands_DPM2Status
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{
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uint32_t dpm2Flags;
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uint8_t CurrPSkip;
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uint8_t CurrPSkipPowerShift;
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uint8_t CurrPSkipTDP;
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uint8_t CurrPSkipOCP;
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uint8_t MaxSPLLIndex;
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uint8_t MinSPLLIndex;
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uint8_t CurrSPLLIndex;
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uint8_t InfSweepMode;
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uint8_t InfSweepDir;
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uint8_t TDPexceeded;
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uint8_t reserved;
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uint8_t SwitchDownThreshold;
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uint32_t SwitchDownCounter;
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uint32_t SysScalingFactor;
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};
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typedef struct PP_SIslands_DPM2Status PP_SIslands_DPM2Status;
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struct PP_SIslands_DPM2Parameters
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{
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uint32_t TDPLimit;
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uint32_t NearTDPLimit;
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uint32_t SafePowerLimit;
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uint32_t PowerBoostLimit;
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uint32_t MinLimitDelta;
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};
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typedef struct PP_SIslands_DPM2Parameters PP_SIslands_DPM2Parameters;
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struct PP_SIslands_PAPMStatus
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{
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uint32_t EstimatedDGPU_T;
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uint32_t EstimatedDGPU_P;
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uint32_t EstimatedAPU_T;
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uint32_t EstimatedAPU_P;
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uint8_t dGPU_T_Limit_Exceeded;
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uint8_t reserved[3];
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};
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typedef struct PP_SIslands_PAPMStatus PP_SIslands_PAPMStatus;
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struct PP_SIslands_PAPMParameters
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{
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uint32_t NearTDPLimitTherm;
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uint32_t NearTDPLimitPAPM;
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uint32_t PlatformPowerLimit;
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uint32_t dGPU_T_Limit;
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uint32_t dGPU_T_Warning;
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uint32_t dGPU_T_Hysteresis;
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};
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typedef struct PP_SIslands_PAPMParameters PP_SIslands_PAPMParameters;
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struct SISLANDS_SMC_SCLK_VALUE
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{
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uint32_t vCG_SPLL_FUNC_CNTL;
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uint32_t vCG_SPLL_FUNC_CNTL_2;
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uint32_t vCG_SPLL_FUNC_CNTL_3;
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uint32_t vCG_SPLL_FUNC_CNTL_4;
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uint32_t vCG_SPLL_SPREAD_SPECTRUM;
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uint32_t vCG_SPLL_SPREAD_SPECTRUM_2;
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uint32_t sclk_value;
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};
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typedef struct SISLANDS_SMC_SCLK_VALUE SISLANDS_SMC_SCLK_VALUE;
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struct SISLANDS_SMC_MCLK_VALUE
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{
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uint32_t vMPLL_FUNC_CNTL;
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uint32_t vMPLL_FUNC_CNTL_1;
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uint32_t vMPLL_FUNC_CNTL_2;
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uint32_t vMPLL_AD_FUNC_CNTL;
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uint32_t vMPLL_DQ_FUNC_CNTL;
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uint32_t vMCLK_PWRMGT_CNTL;
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uint32_t vDLL_CNTL;
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uint32_t vMPLL_SS;
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uint32_t vMPLL_SS2;
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uint32_t mclk_value;
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};
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typedef struct SISLANDS_SMC_MCLK_VALUE SISLANDS_SMC_MCLK_VALUE;
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struct SISLANDS_SMC_VOLTAGE_VALUE
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{
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uint16_t value;
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uint8_t index;
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uint8_t phase_settings;
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};
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typedef struct SISLANDS_SMC_VOLTAGE_VALUE SISLANDS_SMC_VOLTAGE_VALUE;
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struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL
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{
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uint8_t ACIndex;
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uint8_t displayWatermark;
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uint8_t gen2PCIE;
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uint8_t UVDWatermark;
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uint8_t VCEWatermark;
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uint8_t strobeMode;
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uint8_t mcFlags;
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uint8_t padding;
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uint32_t aT;
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uint32_t bSP;
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SISLANDS_SMC_SCLK_VALUE sclk;
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SISLANDS_SMC_MCLK_VALUE mclk;
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SISLANDS_SMC_VOLTAGE_VALUE vddc;
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SISLANDS_SMC_VOLTAGE_VALUE mvdd;
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SISLANDS_SMC_VOLTAGE_VALUE vddci;
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SISLANDS_SMC_VOLTAGE_VALUE std_vddc;
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uint8_t hysteresisUp;
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uint8_t hysteresisDown;
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uint8_t stateFlags;
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uint8_t arbRefreshState;
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uint32_t SQPowerThrottle;
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uint32_t SQPowerThrottle_2;
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uint32_t MaxPoweredUpCU;
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SISLANDS_SMC_VOLTAGE_VALUE high_temp_vddc;
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SISLANDS_SMC_VOLTAGE_VALUE low_temp_vddc;
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uint32_t reserved[2];
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PP_SIslands_Dpm2PerfLevel dpm2;
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};
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#define SISLANDS_SMC_STROBE_RATIO 0x0F
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#define SISLANDS_SMC_STROBE_ENABLE 0x10
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#define SISLANDS_SMC_MC_EDC_RD_FLAG 0x01
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#define SISLANDS_SMC_MC_EDC_WR_FLAG 0x02
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#define SISLANDS_SMC_MC_RTT_ENABLE 0x04
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#define SISLANDS_SMC_MC_STUTTER_EN 0x08
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#define SISLANDS_SMC_MC_PG_EN 0x10
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typedef struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL SISLANDS_SMC_HW_PERFORMANCE_LEVEL;
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struct SISLANDS_SMC_SWSTATE
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{
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uint8_t flags;
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uint8_t levelCount;
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uint8_t padding2;
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uint8_t padding3;
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SISLANDS_SMC_HW_PERFORMANCE_LEVEL levels[];
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};
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typedef struct SISLANDS_SMC_SWSTATE SISLANDS_SMC_SWSTATE;
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struct SISLANDS_SMC_SWSTATE_SINGLE {
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uint8_t flags;
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uint8_t levelCount;
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uint8_t padding2;
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uint8_t padding3;
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SISLANDS_SMC_HW_PERFORMANCE_LEVEL level;
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};
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#define SISLANDS_SMC_VOLTAGEMASK_VDDC 0
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#define SISLANDS_SMC_VOLTAGEMASK_MVDD 1
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#define SISLANDS_SMC_VOLTAGEMASK_VDDCI 2
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#define SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING 3
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#define SISLANDS_SMC_VOLTAGEMASK_MAX 4
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struct SISLANDS_SMC_VOLTAGEMASKTABLE
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{
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uint32_t lowMask[SISLANDS_SMC_VOLTAGEMASK_MAX];
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};
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typedef struct SISLANDS_SMC_VOLTAGEMASKTABLE SISLANDS_SMC_VOLTAGEMASKTABLE;
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#define SISLANDS_MAX_NO_VREG_STEPS 32
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struct SISLANDS_SMC_STATETABLE
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{
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uint8_t thermalProtectType;
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uint8_t systemFlags;
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uint8_t maxVDDCIndexInPPTable;
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uint8_t extraFlags;
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uint32_t lowSMIO[SISLANDS_MAX_NO_VREG_STEPS];
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SISLANDS_SMC_VOLTAGEMASKTABLE voltageMaskTable;
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SISLANDS_SMC_VOLTAGEMASKTABLE phaseMaskTable;
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PP_SIslands_DPM2Parameters dpm2Params;
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struct SISLANDS_SMC_SWSTATE_SINGLE initialState;
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struct SISLANDS_SMC_SWSTATE_SINGLE ACPIState;
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struct SISLANDS_SMC_SWSTATE_SINGLE ULVState;
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SISLANDS_SMC_SWSTATE driverState;
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SISLANDS_SMC_HW_PERFORMANCE_LEVEL dpmLevels[SISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE];
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};
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typedef struct SISLANDS_SMC_STATETABLE SISLANDS_SMC_STATETABLE;
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#define SI_SMC_SOFT_REGISTER_mclk_chg_timeout 0x0
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#define SI_SMC_SOFT_REGISTER_delay_vreg 0xC
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#define SI_SMC_SOFT_REGISTER_delay_acpi 0x28
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#define SI_SMC_SOFT_REGISTER_seq_index 0x5C
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#define SI_SMC_SOFT_REGISTER_mvdd_chg_time 0x60
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#define SI_SMC_SOFT_REGISTER_mclk_switch_lim 0x70
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#define SI_SMC_SOFT_REGISTER_watermark_threshold 0x78
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#define SI_SMC_SOFT_REGISTER_phase_shedding_delay 0x88
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#define SI_SMC_SOFT_REGISTER_ulv_volt_change_delay 0x8C
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#define SI_SMC_SOFT_REGISTER_mc_block_delay 0x98
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#define SI_SMC_SOFT_REGISTER_ticks_per_us 0xA8
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#define SI_SMC_SOFT_REGISTER_crtc_index 0xC4
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#define SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min 0xC8
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#define SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max 0xCC
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#define SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width 0xF4
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#define SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen 0xFC
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#define SI_SMC_SOFT_REGISTER_vr_hot_gpio 0x100
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#define SI_SMC_SOFT_REGISTER_svi_rework_plat_type 0x118
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#define SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd 0x11c
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#define SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc 0x120
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struct PP_SIslands_FanTable
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{
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uint8_t fdo_mode;
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uint8_t padding;
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int16_t temp_min;
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int16_t temp_med;
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int16_t temp_max;
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int16_t slope1;
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int16_t slope2;
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int16_t fdo_min;
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int16_t hys_up;
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int16_t hys_down;
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int16_t hys_slope;
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int16_t temp_resp_lim;
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int16_t temp_curr;
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int16_t slope_curr;
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int16_t pwm_curr;
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uint32_t refresh_period;
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int16_t fdo_max;
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uint8_t temp_src;
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int8_t padding2;
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};
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typedef struct PP_SIslands_FanTable PP_SIslands_FanTable;
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#define SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16
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#define SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES 32
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#define SMC_SISLANDS_SCALE_I 7
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#define SMC_SISLANDS_SCALE_R 12
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struct PP_SIslands_CacConfig
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{
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uint16_t cac_lkge_lut[SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES];
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uint32_t lkge_lut_V0;
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uint32_t lkge_lut_Vstep;
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uint32_t WinTime;
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uint32_t R_LL;
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uint32_t calculation_repeats;
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uint32_t l2numWin_TDP;
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uint32_t dc_cac;
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uint8_t lts_truncate_n;
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uint8_t SHIFT_N;
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uint8_t log2_PG_LKG_SCALE;
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uint8_t cac_temp;
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uint32_t lkge_lut_T0;
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uint32_t lkge_lut_Tstep;
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};
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typedef struct PP_SIslands_CacConfig PP_SIslands_CacConfig;
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#define SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE 16
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#define SMC_SISLANDS_MC_REGISTER_ARRAY_SET_COUNT 20
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struct SMC_SIslands_MCRegisterAddress
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{
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uint16_t s0;
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uint16_t s1;
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};
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typedef struct SMC_SIslands_MCRegisterAddress SMC_SIslands_MCRegisterAddress;
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struct SMC_SIslands_MCRegisterSet
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{
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uint32_t value[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
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};
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typedef struct SMC_SIslands_MCRegisterSet SMC_SIslands_MCRegisterSet;
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struct SMC_SIslands_MCRegisters
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{
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uint8_t last;
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uint8_t reserved[3];
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SMC_SIslands_MCRegisterAddress address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
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SMC_SIslands_MCRegisterSet data[SMC_SISLANDS_MC_REGISTER_ARRAY_SET_COUNT];
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};
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typedef struct SMC_SIslands_MCRegisters SMC_SIslands_MCRegisters;
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struct SMC_SIslands_MCArbDramTimingRegisterSet
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{
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uint32_t mc_arb_dram_timing;
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uint32_t mc_arb_dram_timing2;
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uint8_t mc_arb_rfsh_rate;
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uint8_t mc_arb_burst_time;
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uint8_t padding[2];
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};
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typedef struct SMC_SIslands_MCArbDramTimingRegisterSet SMC_SIslands_MCArbDramTimingRegisterSet;
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struct SMC_SIslands_MCArbDramTimingRegisters
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{
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uint8_t arb_current;
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uint8_t reserved[3];
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SMC_SIslands_MCArbDramTimingRegisterSet data[16];
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};
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typedef struct SMC_SIslands_MCArbDramTimingRegisters SMC_SIslands_MCArbDramTimingRegisters;
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struct SMC_SISLANDS_SPLL_DIV_TABLE
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{
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uint32_t freq[256];
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uint32_t ss[256];
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};
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#define SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK 0x01ffffff
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#define SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT 0
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#define SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK 0xfe000000
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#define SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT 25
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#define SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK 0x000fffff
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#define SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT 0
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#define SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK 0xfff00000
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#define SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT 20
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typedef struct SMC_SISLANDS_SPLL_DIV_TABLE SMC_SISLANDS_SPLL_DIV_TABLE;
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#define SMC_SISLANDS_DTE_MAX_FILTER_STAGES 5
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#define SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE 16
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struct Smc_SIslands_DTE_Configuration
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{
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uint32_t tau[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];
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uint32_t R[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];
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uint32_t K;
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uint32_t T0;
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uint32_t MaxT;
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uint8_t WindowSize;
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uint8_t Tdep_count;
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uint8_t temp_select;
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uint8_t DTE_mode;
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uint8_t T_limits[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
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uint32_t Tdep_tau[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
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uint32_t Tdep_R[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
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uint32_t Tthreshold;
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};
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typedef struct Smc_SIslands_DTE_Configuration Smc_SIslands_DTE_Configuration;
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#define SMC_SISLANDS_DTE_STATUS_FLAG_DTE_ON 1
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#define SISLANDS_SMC_FIRMWARE_HEADER_LOCATION 0x10000
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#define SISLANDS_SMC_FIRMWARE_HEADER_version 0x0
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#define SISLANDS_SMC_FIRMWARE_HEADER_flags 0x4
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#define SISLANDS_SMC_FIRMWARE_HEADER_softRegisters 0xC
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#define SISLANDS_SMC_FIRMWARE_HEADER_stateTable 0x10
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#define SISLANDS_SMC_FIRMWARE_HEADER_fanTable 0x14
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#define SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable 0x18
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#define SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable 0x24
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#define SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable 0x30
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#define SISLANDS_SMC_FIRMWARE_HEADER_spllTable 0x38
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#define SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration 0x40
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#define SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters 0x48
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#pragma pack(pop)
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int amdgpu_si_copy_bytes_to_smc(struct amdgpu_device *adev,
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u32 smc_start_address,
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const u8 *src, u32 byte_count, u32 limit);
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void amdgpu_si_start_smc(struct amdgpu_device *adev);
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void amdgpu_si_reset_smc(struct amdgpu_device *adev);
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int amdgpu_si_program_jump_on_start(struct amdgpu_device *adev);
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void amdgpu_si_smc_clock(struct amdgpu_device *adev, bool enable);
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bool amdgpu_si_is_smc_running(struct amdgpu_device *adev);
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PPSMC_Result amdgpu_si_send_msg_to_smc(struct amdgpu_device *adev, PPSMC_Msg msg);
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PPSMC_Result amdgpu_si_wait_for_smc_inactive(struct amdgpu_device *adev);
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int amdgpu_si_load_smc_ucode(struct amdgpu_device *adev, u32 limit);
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int amdgpu_si_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
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u32 *value, u32 limit);
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int amdgpu_si_write_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
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u32 value, u32 limit);
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#endif
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