4e31b808fa
Now that we actually read registers from QSGMII PCSs, it's important that we have the correct address (instead of hoping that we're the MAC with all the QSGMII PCSs on its bus). This adds nodes for the QSGMII PCSs. They have the same addresses on all SoCs (e.g. if QSGMIIA is present it's used for MACs 1 through 4). Since the first QSGMII PCSs share an address with the SGMII and XFI PCSs, we only add new nodes for PCSs 2-4. This avoids address conflicts on the bus. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Signed-off-by: David S. Miller <davem@davemloft.net>
77 lines
2.7 KiB
Plaintext
77 lines
2.7 KiB
Plaintext
/*
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* QorIQ FMan v3 1g port #5 device tree stub [ controller @ offset 0x400000 ]
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*
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* Copyright 2012 - 2015 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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fman@400000 {
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fman0_rx_0x0d: port@8d000 {
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cell-index = <0xd>;
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compatible = "fsl,fman-v3-port-rx";
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reg = <0x8d000 0x1000>;
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};
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fman0_tx_0x2d: port@ad000 {
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cell-index = <0x2d>;
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compatible = "fsl,fman-v3-port-tx";
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reg = <0xad000 0x1000>;
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};
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ethernet@ea000 {
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cell-index = <5>;
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compatible = "fsl,fman-memac";
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reg = <0xea000 0x1000>;
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fsl,fman-ports = <&fman0_rx_0x0d &fman0_tx_0x2d>;
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ptp-timer = <&ptp_timer0>;
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pcsphy-handle = <&pcsphy5>, <&qsgmiib_pcs1>;
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pcs-handle-names = "sgmii", "qsgmii";
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};
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mdio@e9000 {
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qsgmiib_pcs1: ethernet-pcs@1 {
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compatible = "fsl,lynx-pcs";
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reg = <1>;
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};
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};
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mdio@eb000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
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reg = <0xeb000 0x1000>;
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fsl,erratum-a011043; /* must ignore read errors */
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pcsphy5: ethernet-phy@0 {
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reg = <0x0>;
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};
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};
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};
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