907ba6a195
The M4U IP blocks in mt8183 is MediaTek's generation2 M4U which use the ARM Short-descriptor like mt8173, and most of the HW registers are the same. Here list main differences between mt8183 and mt8173/mt2712: 1) mt8183 has only one M4U HW like mt8173 while mt2712 has two. 2) mt8183 don't have the "bclk" clock, it use the EMI clock instead. 3) mt8183 can support the dram over 4GB, but it doesn't call this "4GB mode". 4) mt8183 pgtable base register(0x0) extend bit[1:0] which represent the bit[33:32] in the physical address of the pgtable base, But the standard ttbr0[1] means the S bit which is enabled defaultly, Hence, we add a mask. 5) mt8183 HW has a GALS modules, SMI should enable "has_gals" support. 6) mt8183 need reset_axi like mt8173. 7) the larb-id in smi-common is remapped. M4U should add its larbid_remap. Signed-off-by: Yong Wu <yong.wu@mediatek.com> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
93 lines
2.0 KiB
C
93 lines
2.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2015-2016 MediaTek Inc.
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* Author: Honghui Zhang <honghui.zhang@mediatek.com>
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*/
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#ifndef _MTK_IOMMU_H_
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#define _MTK_IOMMU_H_
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#include <linux/clk.h>
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#include <linux/component.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/io-pgtable.h>
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#include <linux/iommu.h>
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#include <linux/list.h>
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#include <linux/spinlock.h>
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#include <soc/mediatek/smi.h>
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struct mtk_iommu_suspend_reg {
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u32 standard_axi_mode;
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u32 dcm_dis;
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u32 ctrl_reg;
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u32 int_control0;
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u32 int_main_control;
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u32 ivrp_paddr;
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};
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enum mtk_iommu_plat {
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M4U_MT2701,
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M4U_MT2712,
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M4U_MT8173,
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M4U_MT8183,
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};
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struct mtk_iommu_plat_data {
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enum mtk_iommu_plat m4u_plat;
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bool has_4gb_mode;
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/* HW will use the EMI clock if there isn't the "bclk". */
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bool has_bclk;
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bool has_vld_pa_rng;
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bool reset_axi;
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unsigned char larbid_remap[MTK_LARB_NR_MAX];
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};
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struct mtk_iommu_domain;
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struct mtk_iommu_data {
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void __iomem *base;
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int irq;
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struct device *dev;
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struct clk *bclk;
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phys_addr_t protect_base; /* protect memory base */
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struct mtk_iommu_suspend_reg reg;
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struct mtk_iommu_domain *m4u_dom;
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struct iommu_group *m4u_group;
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struct mtk_smi_iommu smi_imu; /* SMI larb iommu info */
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bool enable_4GB;
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bool tlb_flush_active;
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struct iommu_device iommu;
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const struct mtk_iommu_plat_data *plat_data;
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struct list_head list;
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};
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static inline int compare_of(struct device *dev, void *data)
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{
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return dev->of_node == data;
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}
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static inline void release_of(struct device *dev, void *data)
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{
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of_node_put(data);
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}
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static inline int mtk_iommu_bind(struct device *dev)
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{
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struct mtk_iommu_data *data = dev_get_drvdata(dev);
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return component_bind_all(dev, &data->smi_imu);
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}
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static inline void mtk_iommu_unbind(struct device *dev)
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{
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struct mtk_iommu_data *data = dev_get_drvdata(dev);
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component_unbind_all(dev, &data->smi_imu);
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}
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#endif
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