ea3de9ce8a
We don't have enough space for these all in ELF_HWCAP{,2} and there's no
system call that quite does this, so let's just provide an arch-specific
one to probe for hardware capabilities. This currently just provides
m{arch,imp,vendor}id, but with the key-value pairs we can pass more in
the future.
Co-developed-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Evan Green <evan@rivosinc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Tested-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Reviewed-by: Paul Walmsley <paul.walmsley@sifive.com>
Link: https://lore.kernel.org/r/20230407231103.2622178-3-evan@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
55 lines
2.1 KiB
C
55 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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/*
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* Copyright (C) 2018 David Abdurachmanov <david.abdurachmanov@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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#if defined(__LP64__) && !defined(__SYSCALL_COMPAT)
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#define __ARCH_WANT_NEW_STAT
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#define __ARCH_WANT_SET_GET_RLIMIT
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#endif /* __LP64__ */
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#define __ARCH_WANT_SYS_CLONE3
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#define __ARCH_WANT_MEMFD_SECRET
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#include <asm-generic/unistd.h>
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/*
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* Allows the instruction cache to be flushed from userspace. Despite RISC-V
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* having a direct 'fence.i' instruction available to userspace (which we
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* can't trap!), that's not actually viable when running on Linux because the
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* kernel might schedule a process on another hart. There is no way for
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* userspace to handle this without invoking the kernel (as it doesn't know the
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* thread->hart mappings), so we've defined a RISC-V specific system call to
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* flush the instruction cache.
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*
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* __NR_riscv_flush_icache is defined to flush the instruction cache over an
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* address range, with the flush applying to either all threads or just the
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* caller. We don't currently do anything with the address range, that's just
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* in there for forwards compatibility.
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*/
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#ifndef __NR_riscv_flush_icache
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#define __NR_riscv_flush_icache (__NR_arch_specific_syscall + 15)
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#endif
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__SYSCALL(__NR_riscv_flush_icache, sys_riscv_flush_icache)
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/*
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* Allows userspace to query the kernel for CPU architecture and
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* microarchitecture details across a given set of CPUs.
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*/
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#ifndef __NR_riscv_hwprobe
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#define __NR_riscv_hwprobe (__NR_arch_specific_syscall + 14)
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#endif
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__SYSCALL(__NR_riscv_hwprobe, sys_riscv_hwprobe)
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