Catalin Marinas 9141300a58 arm64: Provide read/write fault information in compat signal handlers ... For AArch32, bit 11 (WnR) of the FSR/ESR register is set when the fault was caused by a write access and applications like Qemu rely on such information being provided in sigcontext. This patch introduces the ESR_EL1 tracking for the arm64 kernel faults and sets bit 11 accordingly in compat sigcontext. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>		2014-05-09 15:47:47 +01:00
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asm	arm64: Provide read/write fault information in compat signal handlers	2014-05-09 15:47:47 +01:00
uapi/asm	ARM64: perf: add support for perf registers API	2014-03-13 11:22:37 +00:00