linux

iv/linux

History

Jerome Brunet 914e6e80b3 clk: meson: gxbb: Add sd_emmc clk0 clocks

Input source 0 of the mmc controllers is not directly xtal, as currently
described in DT. Each controller is fed by a composite clock (the usual
mux, divider and gate). The muxes inputs are the xtal (default) and the
fclk_div clocks. These parents, along with the divider, should be able to
provide the necessary rates for mmc and nand operation.

The input muxes should also be able to take mpll2, mpll3 and gp0_pll but
these are precious clocks, needed for other usage. It is better if the
mmc does not use these them. For this reason, mpll2, mpll3 and gp0_pll is
not listed among the possible parents.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>

2017-08-04 18:02:00 +02:00

clk-audio-divider.c

clk: meson: add audio clock divider support

2017-04-07 16:50:44 +02:00

clk-cpu.c

clk: meson8b: clean up cpu clocks

2016-06-22 18:02:35 -07:00

clk-mpll.c

clk: meson: mpll: use 64bit math in rate_from_params

2017-04-07 17:45:30 +02:00

clk-pll.c

clk: meson: Add support for parameters for specific PLLs