0bfbc914d9
* Support for byte/half-word compare-and-exchange, emulated via LR/SC loops. * Support for Rust. * Support for Zihintpause in hwprobe. * Support for the PR_RISCV_SET_ICACHE_FLUSH_CTX prctl(). * Support for lockless lockrefs. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmZN/hcTHHBhbG1lckBk YWJiZWx0LmNvbQAKCRAuExnzX7sYiVrGEACUT3gsbTx1q7fa11iQNxOjVkpl66Qn 7+kI+V9xt5+GuH2EjJk6AsSNHPKeQ8totbSTA8AZjINFvgVjXslN+DPpcjCFKvnh NN5/Lyd64X0PZMsxGWlN9SHTFWf2b7lalCnY51BlX/IpBbHWc/no9XUsPSVixx6u 9q+JoS3D1DDV92nGcA/UK9ICCsDcf4omWgZW7KbjnVWnuY9jt4ctTy11jtF2RM9R Z9KAWh0RqPzjz0vNbBBf9Iw7E4jt/Px6HDYPfZAiE2dVsCTHjdsC7TcGRYXzKt6F 4q9zg8kzwvUG5GaBl7/XprXO1vaeOUmPcTVoE7qlRkSdkknRH/iBz1P4hk+r0fze f+h5ZUV/oJP7vDb+vHm/BExtGufgLuJ2oMA2Bp9qI17EMcMsGiRMt7DsBMEafWDk bNrFcJdqqYBz6HxfTwzNH5ErxfS/59PuwYl913BTSOH//raCZCFXOfyrSICH7qXd UFOLLmBpMuApLa8ayFeI9Mp3flWfbdQHR52zLRLiUvlpWNEDKrNQN417juVwTXF0 DYkjJDhFPLfFOr/sJBboftOMOUdA9c/CJepY9o4kPvBXUvPtRHN1jdXDNSCVDZRb nErnsJ9rv0PzfxQU7Xjhd2QmCMeMlbCQDpXAKKETyyimpTbgF33rovN0i5ixX3m4 KG6RvKDubOzZdA== =YLoD -----END PGP SIGNATURE----- Merge tag 'riscv-for-linus-6.10-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Palmer Dabbelt: - Add byte/half-word compare-and-exchange, emulated via LR/SC loops - Support for Rust - Support for Zihintpause in hwprobe - Add PR_RISCV_SET_ICACHE_FLUSH_CTX prctl() - Support lockless lockrefs * tag 'riscv-for-linus-6.10-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (42 commits) riscv: defconfig: Enable CONFIG_CLK_SOPHGO_CV1800 riscv: select ARCH_HAS_FAST_MULTIPLIER riscv: mm: still create swiotlb buffer for kmalloc() bouncing if required riscv: Annotate pgtable_l{4,5}_enabled with __ro_after_init riscv: Remove redundant CONFIG_64BIT from pgtable_l{4,5}_enabled riscv: mm: Always use an ASID to flush mm contexts riscv: mm: Preserve global TLB entries when switching contexts riscv: mm: Make asid_bits a local variable riscv: mm: Use a fixed layout for the MM context ID riscv: mm: Introduce cntx2asid/cntx2version helper macros riscv: Avoid TLB flush loops when affected by SiFive CIP-1200 riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma riscv: mm: Combine the SMP and UP TLB flush code riscv: Only send remote fences when some other CPU is online riscv: mm: Broadcast kernel TLB flushes only when needed riscv: Use IPIs for remote cache/TLB flushes by default riscv: Factor out page table TLB synchronization riscv: Flush the instruction cache during SMP bringup riscv: hwprobe: export Zihintpause ISA extension riscv: misaligned: remove CONFIG_RISCV_M_MODE specific code ...
193 lines
5.7 KiB
Rust
193 lines
5.7 KiB
Rust
// SPDX-License-Identifier: GPL-2.0
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//! The custom target specification file generator for `rustc`.
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//!
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//! To configure a target from scratch, a JSON-encoded file has to be passed
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//! to `rustc` (introduced in [RFC 131]). These options and the file itself are
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//! unstable. Eventually, `rustc` should provide a way to do this in a stable
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//! manner. For instance, via command-line arguments. Therefore, this file
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//! should avoid using keys which can be set via `-C` or `-Z` options.
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//!
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//! [RFC 131]: https://rust-lang.github.io/rfcs/0131-target-specification.html
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use std::{
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collections::HashMap,
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fmt::{Display, Formatter, Result},
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io::BufRead,
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};
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enum Value {
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Boolean(bool),
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Number(i32),
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String(String),
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Object(Object),
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}
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type Object = Vec<(String, Value)>;
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/// Minimal "almost JSON" generator (e.g. no `null`s, no arrays, no escaping),
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/// enough for this purpose.
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impl Display for Value {
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fn fmt(&self, formatter: &mut Formatter<'_>) -> Result {
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match self {
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Value::Boolean(boolean) => write!(formatter, "{}", boolean),
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Value::Number(number) => write!(formatter, "{}", number),
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Value::String(string) => write!(formatter, "\"{}\"", string),
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Value::Object(object) => {
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formatter.write_str("{")?;
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if let [ref rest @ .., ref last] = object[..] {
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for (key, value) in rest {
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write!(formatter, "\"{}\": {},", key, value)?;
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}
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write!(formatter, "\"{}\": {}", last.0, last.1)?;
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}
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formatter.write_str("}")
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}
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}
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}
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}
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struct TargetSpec(Object);
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impl TargetSpec {
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fn new() -> TargetSpec {
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TargetSpec(Vec::new())
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}
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}
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trait Push<T> {
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fn push(&mut self, key: &str, value: T);
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}
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impl Push<bool> for TargetSpec {
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fn push(&mut self, key: &str, value: bool) {
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self.0.push((key.to_string(), Value::Boolean(value)));
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}
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}
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impl Push<i32> for TargetSpec {
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fn push(&mut self, key: &str, value: i32) {
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self.0.push((key.to_string(), Value::Number(value)));
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}
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}
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impl Push<String> for TargetSpec {
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fn push(&mut self, key: &str, value: String) {
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self.0.push((key.to_string(), Value::String(value)));
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}
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}
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impl Push<&str> for TargetSpec {
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fn push(&mut self, key: &str, value: &str) {
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self.push(key, value.to_string());
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}
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}
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impl Push<Object> for TargetSpec {
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fn push(&mut self, key: &str, value: Object) {
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self.0.push((key.to_string(), Value::Object(value)));
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}
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}
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impl Display for TargetSpec {
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fn fmt(&self, formatter: &mut Formatter<'_>) -> Result {
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// We add some newlines for clarity.
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formatter.write_str("{\n")?;
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if let [ref rest @ .., ref last] = self.0[..] {
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for (key, value) in rest {
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write!(formatter, " \"{}\": {},\n", key, value)?;
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}
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write!(formatter, " \"{}\": {}\n", last.0, last.1)?;
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}
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formatter.write_str("}")
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}
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}
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struct KernelConfig(HashMap<String, String>);
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impl KernelConfig {
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/// Parses `include/config/auto.conf` from `stdin`.
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fn from_stdin() -> KernelConfig {
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let mut result = HashMap::new();
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let stdin = std::io::stdin();
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let mut handle = stdin.lock();
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let mut line = String::new();
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loop {
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line.clear();
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if handle.read_line(&mut line).unwrap() == 0 {
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break;
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}
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if line.starts_with('#') {
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continue;
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}
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let (key, value) = line.split_once('=').expect("Missing `=` in line.");
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result.insert(key.to_string(), value.trim_end_matches('\n').to_string());
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}
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KernelConfig(result)
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}
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/// Does the option exist in the configuration (any value)?
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///
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/// The argument must be passed without the `CONFIG_` prefix.
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/// This avoids repetition and it also avoids `fixdep` making us
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/// depend on it.
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fn has(&self, option: &str) -> bool {
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let option = "CONFIG_".to_owned() + option;
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self.0.contains_key(&option)
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}
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}
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fn main() {
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let cfg = KernelConfig::from_stdin();
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let mut ts = TargetSpec::new();
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// `llvm-target`s are taken from `scripts/Makefile.clang`.
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if cfg.has("ARM64") {
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panic!("arm64 uses the builtin rustc aarch64-unknown-none target");
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} else if cfg.has("RISCV") {
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if cfg.has("64BIT") {
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panic!("64-bit RISC-V uses the builtin rustc riscv64-unknown-none-elf target");
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} else {
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panic!("32-bit RISC-V is an unsupported architecture");
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}
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} else if cfg.has("X86_64") {
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ts.push("arch", "x86_64");
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ts.push(
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"data-layout",
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"e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128",
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);
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let mut features = "-3dnow,-3dnowa,-mmx,+soft-float".to_string();
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if cfg.has("MITIGATION_RETPOLINE") {
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features += ",+retpoline-external-thunk";
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}
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ts.push("features", features);
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ts.push("llvm-target", "x86_64-linux-gnu");
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ts.push("target-pointer-width", "64");
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} else if cfg.has("LOONGARCH") {
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panic!("loongarch uses the builtin rustc loongarch64-unknown-none-softfloat target");
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} else {
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panic!("Unsupported architecture");
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}
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ts.push("emit-debug-gdb-scripts", false);
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ts.push("frame-pointer", "may-omit");
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ts.push(
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"stack-probes",
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vec![("kind".to_string(), Value::String("none".to_string()))],
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);
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// Everything else is LE, whether `CPU_LITTLE_ENDIAN` is declared or not
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// (e.g. x86). It is also `rustc`'s default.
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if cfg.has("CPU_BIG_ENDIAN") {
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ts.push("target-endian", "big");
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}
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println!("{}", ts);
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}
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