linux/arch/riscv/include/asm/cpu_ops_sbi.h
Atish Patra 9a2451f186
RISC-V: Avoid using per cpu array for ordered booting
Currently both order booting and spinwait approach uses a per cpu
array to update stack & task pointer. This approach will not work for the
following cases.
1. If NR_CPUs are configured to be less than highest hart id.
2. A platform has sparse hartid.

This issue can be fixed for ordered booting as the booting cpu brings up
one cpu at a time using SBI HSM extension which has opaque parameter
that is unused until now.

Introduce a common secondary boot data structure that can store the stack
and task pointer. Secondary harts will use this data while booting up
to setup the sp & tp.

Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-01-20 09:26:59 -08:00

26 lines
560 B
C

/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2021 by Rivos Inc.
*/
#ifndef __ASM_CPU_OPS_SBI_H
#define __ASM_CPU_OPS_SBI_H
#ifndef __ASSEMBLY__
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/threads.h>
/**
* struct sbi_hart_boot_data - Hart specific boot used during booting and
* cpu hotplug.
* @task_ptr: A pointer to the hart specific tp
* @stack_ptr: A pointer to the hart specific sp
*/
struct sbi_hart_boot_data {
void *task_ptr;
void *stack_ptr;
};
#endif
#endif /* ifndef __ASM_CPU_OPS_SBI_H */