bff3ff5254
For certain SiFive CPUs, "sfence.vma addr" cannot exactly flush addr from TLB in the particular cases. The details could be found here: https://sifive.cdn.prismic.io/sifive/167a1a56-03f4-4615-a79e-b2a86153148f_FU740_errata_20210205.pdf In order to ensure the functionality, this patch uses the Alternative scheme to replace all "sfence.vma addr" with "sfence.vma" at runtime. Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
40 lines
1.0 KiB
C
40 lines
1.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2021 Sifive.
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*/
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#ifndef ASM_ERRATA_LIST_H
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#define ASM_ERRATA_LIST_H
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#include <asm/alternative.h>
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#include <asm/vendorid_list.h>
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#ifdef CONFIG_ERRATA_SIFIVE
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#define ERRATA_SIFIVE_CIP_453 0
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#define ERRATA_SIFIVE_CIP_1200 1
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#define ERRATA_SIFIVE_NUMBER 2
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#endif
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#ifdef __ASSEMBLY__
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#define ALT_INSN_FAULT(x) \
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ALTERNATIVE(__stringify(RISCV_PTR do_trap_insn_fault), \
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__stringify(RISCV_PTR sifive_cip_453_insn_fault_trp), \
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SIFIVE_VENDOR_ID, ERRATA_SIFIVE_CIP_453, \
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CONFIG_ERRATA_SIFIVE_CIP_453)
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#define ALT_PAGE_FAULT(x) \
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ALTERNATIVE(__stringify(RISCV_PTR do_page_fault), \
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__stringify(RISCV_PTR sifive_cip_453_page_fault_trp), \
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SIFIVE_VENDOR_ID, ERRATA_SIFIVE_CIP_453, \
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CONFIG_ERRATA_SIFIVE_CIP_453)
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#else /* !__ASSEMBLY__ */
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#define ALT_FLUSH_TLB_PAGE(x) \
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asm(ALTERNATIVE("sfence.vma %0", "sfence.vma", SIFIVE_VENDOR_ID, \
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ERRATA_SIFIVE_CIP_1200, CONFIG_ERRATA_SIFIVE_CIP_1200) \
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: : "r" (addr) : "memory")
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#endif /* __ASSEMBLY__ */
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#endif
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