Stefan Agner 92a847e360 clk: imx7d: fix ahb clock mux 1
The clock parent of the AHB root clock when using mux option 1
is the SYS PLL 270MHz clock. This is specified in  Table 5-11
Clock Root Table of the i.MX 7Dual Applications Processor
Reference Manual.

While it could be a documentation error, the 270MHz parent is
also mentioned in the boot ROM configuration in Table 6-28: The
clock is by default at 135MHz due to a POST_PODF value of 1
(=> divider of 2).

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-05-03 20:35:38 +08:00
..
2015-11-10 15:00:03 -08:00
2016-05-03 20:35:38 +08:00
2015-07-20 11:11:36 -07:00
2015-12-01 21:44:22 +01:00
2016-03-03 11:26:42 -08:00
2016-03-02 17:44:59 -08:00
2016-03-04 12:52:10 -08:00
2016-03-04 12:53:53 -08:00
2016-03-02 17:46:29 -08:00
2016-03-02 17:46:55 -08:00
2016-03-02 17:47:19 -08:00
2016-03-20 15:08:45 -07:00
2016-03-02 17:48:03 -08:00
2016-03-02 17:48:26 -08:00
2015-07-20 11:11:32 -07:00
2015-05-21 11:55:05 -07:00
2016-03-02 17:48:47 -08:00
2016-03-20 15:08:45 -07:00
2015-07-20 11:11:22 -07:00
2016-03-03 11:27:48 -08:00
2015-07-20 11:11:33 -07:00
2016-03-02 17:50:08 -08:00
2015-11-30 13:00:54 -08:00
2015-07-20 10:53:00 -07:00
2016-03-02 17:50:32 -08:00
2016-03-02 17:50:58 -08:00
2015-07-20 10:53:04 -07:00
2015-07-20 10:53:05 -07:00
2016-03-01 16:23:40 -08:00