92c8e49620
The IRQ_SPI() macro is not available in the driver when building with sparse IRQs or multiplatform, so let's move all users of this into one function that we can leave out when building DT-only. Signed-off-by: Arnd Bergmann <arnd@arnd.de> Cc: Thomas Gleixner <tglx@linutronix.de>
276 lines
6.7 KiB
C
276 lines
6.7 KiB
C
/*
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Combiner irqchip for EXYNOS
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/err.h>
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#include <linux/export.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/irqdomain.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <asm/mach/irq.h>
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#ifdef CONFIG_EXYNOS_ATAGS
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#include <plat/cpu.h>
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#endif
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#include "irqchip.h"
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#define COMBINER_ENABLE_SET 0x0
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#define COMBINER_ENABLE_CLEAR 0x4
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#define COMBINER_INT_STATUS 0xC
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#define IRQ_IN_COMBINER 8
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static DEFINE_SPINLOCK(irq_controller_lock);
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struct combiner_chip_data {
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unsigned int irq_offset;
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unsigned int irq_mask;
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void __iomem *base;
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unsigned int parent_irq;
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};
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static struct irq_domain *combiner_irq_domain;
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static inline void __iomem *combiner_base(struct irq_data *data)
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{
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struct combiner_chip_data *combiner_data =
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irq_data_get_irq_chip_data(data);
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return combiner_data->base;
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}
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static void combiner_mask_irq(struct irq_data *data)
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{
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u32 mask = 1 << (data->hwirq % 32);
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__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
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}
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static void combiner_unmask_irq(struct irq_data *data)
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{
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u32 mask = 1 << (data->hwirq % 32);
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__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
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}
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static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
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{
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struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
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struct irq_chip *chip = irq_get_chip(irq);
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unsigned int cascade_irq, combiner_irq;
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unsigned long status;
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chained_irq_enter(chip, desc);
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spin_lock(&irq_controller_lock);
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status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
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spin_unlock(&irq_controller_lock);
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status &= chip_data->irq_mask;
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if (status == 0)
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goto out;
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combiner_irq = __ffs(status);
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cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
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if (unlikely(cascade_irq >= NR_IRQS))
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do_bad_IRQ(cascade_irq, desc);
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else
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generic_handle_irq(cascade_irq);
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out:
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chained_irq_exit(chip, desc);
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}
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#ifdef CONFIG_SMP
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static int combiner_set_affinity(struct irq_data *d,
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const struct cpumask *mask_val, bool force)
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{
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struct combiner_chip_data *chip_data = irq_data_get_irq_chip_data(d);
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struct irq_chip *chip = irq_get_chip(chip_data->parent_irq);
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struct irq_data *data = irq_get_irq_data(chip_data->parent_irq);
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if (chip && chip->irq_set_affinity)
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return chip->irq_set_affinity(data, mask_val, force);
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else
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return -EINVAL;
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}
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#endif
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static struct irq_chip combiner_chip = {
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.name = "COMBINER",
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.irq_mask = combiner_mask_irq,
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.irq_unmask = combiner_unmask_irq,
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#ifdef CONFIG_SMP
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.irq_set_affinity = combiner_set_affinity,
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#endif
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};
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static void __init combiner_cascade_irq(struct combiner_chip_data *combiner_data,
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unsigned int irq)
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{
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if (irq_set_handler_data(irq, combiner_data) != 0)
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BUG();
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irq_set_chained_handler(irq, combiner_handle_cascade_irq);
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}
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static void __init combiner_init_one(struct combiner_chip_data *combiner_data,
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unsigned int combiner_nr,
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void __iomem *base, unsigned int irq)
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{
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combiner_data->base = base;
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combiner_data->irq_offset = irq_find_mapping(
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combiner_irq_domain, combiner_nr * IRQ_IN_COMBINER);
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combiner_data->irq_mask = 0xff << ((combiner_nr % 4) << 3);
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combiner_data->parent_irq = irq;
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/* Disable all interrupts */
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__raw_writel(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR);
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}
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#ifdef CONFIG_OF
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static int combiner_irq_domain_xlate(struct irq_domain *d,
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struct device_node *controller,
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const u32 *intspec, unsigned int intsize,
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unsigned long *out_hwirq,
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unsigned int *out_type)
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{
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if (d->of_node != controller)
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return -EINVAL;
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if (intsize < 2)
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return -EINVAL;
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*out_hwirq = intspec[0] * IRQ_IN_COMBINER + intspec[1];
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*out_type = 0;
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return 0;
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}
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#else
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static int combiner_irq_domain_xlate(struct irq_domain *d,
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struct device_node *controller,
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const u32 *intspec, unsigned int intsize,
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unsigned long *out_hwirq,
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unsigned int *out_type)
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{
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return -EINVAL;
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}
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#endif
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static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hw)
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{
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struct combiner_chip_data *combiner_data = d->host_data;
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irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq);
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irq_set_chip_data(irq, &combiner_data[hw >> 3]);
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set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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return 0;
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}
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static struct irq_domain_ops combiner_irq_domain_ops = {
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.xlate = combiner_irq_domain_xlate,
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.map = combiner_irq_domain_map,
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};
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static unsigned int combiner_lookup_irq(int group)
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{
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#ifdef CONFIG_EXYNOS_ATAGS
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if (group < EXYNOS4210_MAX_COMBINER_NR || soc_is_exynos5250())
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return IRQ_SPI(group);
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switch (group) {
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case 16:
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return IRQ_SPI(107);
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case 17:
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return IRQ_SPI(108);
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case 18:
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return IRQ_SPI(48);
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case 19:
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return IRQ_SPI(42);
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}
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#endif
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return 0;
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}
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void __init combiner_init(void __iomem *combiner_base,
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struct device_node *np,
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unsigned int max_nr)
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{
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int i, irq, irq_base;
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unsigned int nr_irq;
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struct combiner_chip_data *combiner_data;
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nr_irq = max_nr * IRQ_IN_COMBINER;
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irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
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if (IS_ERR_VALUE(irq_base)) {
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irq_base = COMBINER_IRQ(0, 0);
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pr_warning("%s: irq desc alloc failed. Continuing with %d as linux irq base\n", __func__, irq_base);
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}
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combiner_data = kcalloc(max_nr, sizeof (*combiner_data), GFP_KERNEL);
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if (!combiner_data) {
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pr_warning("%s: could not allocate combiner data\n", __func__);
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return;
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}
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combiner_irq_domain = irq_domain_add_legacy(np, nr_irq, irq_base, 0,
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&combiner_irq_domain_ops, combiner_data);
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if (WARN_ON(!combiner_irq_domain)) {
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pr_warning("%s: irq domain init failed\n", __func__);
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return;
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}
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for (i = 0; i < max_nr; i++) {
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#ifdef CONFIG_OF
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if (np)
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irq = irq_of_parse_and_map(np, i);
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else
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#endif
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irq = combiner_lookup_irq(i);
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combiner_init_one(&combiner_data[i], i,
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combiner_base + (i >> 2) * 0x10, irq);
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combiner_cascade_irq(&combiner_data[i], irq);
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}
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}
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#ifdef CONFIG_OF
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static int __init combiner_of_init(struct device_node *np,
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struct device_node *parent)
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{
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void __iomem *combiner_base;
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unsigned int max_nr = 20;
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combiner_base = of_iomap(np, 0);
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if (!combiner_base) {
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pr_err("%s: failed to map combiner registers\n", __func__);
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return -ENXIO;
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}
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if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
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pr_info("%s: number of combiners not specified, "
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"setting default as %d.\n",
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__func__, max_nr);
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}
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combiner_init(combiner_base, np, max_nr);
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return 0;
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}
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IRQCHIP_DECLARE(exynos4210_combiner, "samsung,exynos4210-combiner",
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combiner_of_init);
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#endif
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