c6536676c7
gets rid of the LAZY_GS stuff and a lot of code. - Add an insn_decode() API which all users of the instruction decoder should preferrably use. Its goal is to keep the details of the instruction decoder away from its users and simplify and streamline how one decodes insns in the kernel. Convert its users to it. - kprobes improvements and fixes - Set the maximum DIE per package variable on Hygon - Rip out the dynamic NOP selection and simplify all the machinery around selecting NOPs. Use the simplified NOPs in objtool now too. - Add Xeon Sapphire Rapids to list of CPUs that support PPIN - Simplify the retpolines by folding the entire thing into an alternative now that objtool can handle alternatives with stack ops. Then, have objtool rewrite the call to the retpoline with the alternative which then will get patched at boot time. - Document Intel uarch per models in intel-family.h - Make Sub-NUMA Clustering topology the default and Cluster-on-Die the exception on Intel. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEzv7L6UO9uDPlPSfHEsHwGGHeVUoFAmCHyJQACgkQEsHwGGHe VUpjiRAAwPZdwwp08ypZuMHR4EhLNru6gYhbAoALGgtYnQjLtn5onQhIeieK+R4L cmZpxHT9OFp5dXHk4kwygaQBsD4pPOiIpm60kye1dN3cSbOORRdkwEoQMpKMZ+5Y kvVsmn7lrwRbp600KdE4G6L5+N6gEgr0r6fMFWWGK3mgVAyCzPexVHgydcp131ch iYMo6/pPDcNkcV/hboVKgx7GISdQ7L356L1MAIW/Sxtw6uD/X4qGYW+kV2OQg9+t nQDaAo7a8Jqlop5W5TQUdMLKQZ1xK8SFOSX/nTS15DZIOBQOGgXR7Xjywn1chBH/ PHLwM5s4XF6NT5VlIA8tXNZjWIZTiBdldr1kJAmdDYacrtZVs2LWSOC0ilXsd08Z EWtvcpHfHEqcuYJlcdALuXY8xDWqf6Q2F7BeadEBAxwnnBg+pAEoLXI/1UwWcmsj wpaZTCorhJpYo2pxXckVdHz2z0LldDCNOXOjjaWU8tyaOBKEK6MgAaYU7e0yyENv mVc9n5+WuvXuivC6EdZ94Pcr/KQsd09ezpJYcVfMDGv58YZrb6XIEELAJIBTu2/B Ua8QApgRgetx+1FKb8X6eGjPl0p40qjD381TADb4rgETPb1AgKaQflmrSTIik+7p O+Eo/4x/GdIi9jFk3K+j4mIznRbUX0cheTJgXoiI4zXML9Jv94w= =bm4S -----END PGP SIGNATURE----- Merge tag 'x86_core_for_v5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 updates from Borislav Petkov: - Turn the stack canary into a normal __percpu variable on 32-bit which gets rid of the LAZY_GS stuff and a lot of code. - Add an insn_decode() API which all users of the instruction decoder should preferrably use. Its goal is to keep the details of the instruction decoder away from its users and simplify and streamline how one decodes insns in the kernel. Convert its users to it. - kprobes improvements and fixes - Set the maximum DIE per package variable on Hygon - Rip out the dynamic NOP selection and simplify all the machinery around selecting NOPs. Use the simplified NOPs in objtool now too. - Add Xeon Sapphire Rapids to list of CPUs that support PPIN - Simplify the retpolines by folding the entire thing into an alternative now that objtool can handle alternatives with stack ops. Then, have objtool rewrite the call to the retpoline with the alternative which then will get patched at boot time. - Document Intel uarch per models in intel-family.h - Make Sub-NUMA Clustering topology the default and Cluster-on-Die the exception on Intel. * tag 'x86_core_for_v5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (53 commits) x86, sched: Treat Intel SNC topology as default, COD as exception x86/cpu: Comment Skylake server stepping too x86/cpu: Resort and comment Intel models objtool/x86: Rewrite retpoline thunk calls objtool: Skip magical retpoline .altinstr_replacement objtool: Cache instruction relocs objtool: Keep track of retpoline call sites objtool: Add elf_create_undef_symbol() objtool: Extract elf_symbol_add() objtool: Extract elf_strtab_concat() objtool: Create reloc sections implicitly objtool: Add elf_create_reloc() helper objtool: Rework the elf_rebuild_reloc_section() logic objtool: Fix static_call list generation objtool: Handle per arch retpoline naming objtool: Correctly handle retpoline thunk calls x86/retpoline: Simplify retpolines x86/alternatives: Optimize optimize_nops() x86: Add insn_decode_kernel() x86/kprobes: Move 'inline' to the beginning of the kprobe_is_ss() declaration ...
166 lines
3.9 KiB
ArmAsm
166 lines
3.9 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright C 2016, Oracle and/or its affiliates. All rights reserved.
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*/
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.code32
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.text
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#define _pa(x) ((x) - __START_KERNEL_map)
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#include <linux/elfnote.h>
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <asm/segment.h>
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#include <asm/asm.h>
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#include <asm/boot.h>
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#include <asm/processor-flags.h>
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#include <asm/msr.h>
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#include <asm/nospec-branch.h>
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#include <xen/interface/elfnote.h>
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__HEAD
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/*
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* Entry point for PVH guests.
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*
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* Xen ABI specifies the following register state when we come here:
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*
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* - `ebx`: contains the physical memory address where the loader has placed
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* the boot start info structure.
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* - `cr0`: bit 0 (PE) must be set. All the other writeable bits are cleared.
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* - `cr4`: all bits are cleared.
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* - `cs `: must be a 32-bit read/execute code segment with a base of `0`
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* and a limit of `0xFFFFFFFF`. The selector value is unspecified.
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* - `ds`, `es`: must be a 32-bit read/write data segment with a base of
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* `0` and a limit of `0xFFFFFFFF`. The selector values are all
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* unspecified.
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* - `tr`: must be a 32-bit TSS (active) with a base of '0' and a limit
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* of '0x67'.
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* - `eflags`: bit 17 (VM) must be cleared. Bit 9 (IF) must be cleared.
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* Bit 8 (TF) must be cleared. Other bits are all unspecified.
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*
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* All other processor registers and flag bits are unspecified. The OS is in
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* charge of setting up it's own stack, GDT and IDT.
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*/
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#define PVH_GDT_ENTRY_CS 1
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#define PVH_GDT_ENTRY_DS 2
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#define PVH_CS_SEL (PVH_GDT_ENTRY_CS * 8)
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#define PVH_DS_SEL (PVH_GDT_ENTRY_DS * 8)
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SYM_CODE_START_LOCAL(pvh_start_xen)
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cld
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lgdt (_pa(gdt))
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mov $PVH_DS_SEL,%eax
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mov %eax,%ds
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mov %eax,%es
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mov %eax,%ss
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/* Stash hvm_start_info. */
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mov $_pa(pvh_start_info), %edi
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mov %ebx, %esi
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mov _pa(pvh_start_info_sz), %ecx
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shr $2,%ecx
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rep
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movsl
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mov $_pa(early_stack_end), %esp
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/* Enable PAE mode. */
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mov %cr4, %eax
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orl $X86_CR4_PAE, %eax
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mov %eax, %cr4
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#ifdef CONFIG_X86_64
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/* Enable Long mode. */
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mov $MSR_EFER, %ecx
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rdmsr
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btsl $_EFER_LME, %eax
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wrmsr
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/* Enable pre-constructed page tables. */
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mov $_pa(init_top_pgt), %eax
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mov %eax, %cr3
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mov $(X86_CR0_PG | X86_CR0_PE), %eax
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mov %eax, %cr0
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/* Jump to 64-bit mode. */
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ljmp $PVH_CS_SEL, $_pa(1f)
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/* 64-bit entry point. */
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.code64
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1:
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/* Set base address in stack canary descriptor. */
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mov $MSR_GS_BASE,%ecx
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mov $_pa(canary), %eax
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xor %edx, %edx
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wrmsr
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call xen_prepare_pvh
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/* startup_64 expects boot_params in %rsi. */
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mov $_pa(pvh_bootparams), %rsi
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mov $_pa(startup_64), %rax
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ANNOTATE_RETPOLINE_SAFE
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jmp *%rax
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#else /* CONFIG_X86_64 */
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call mk_early_pgtbl_32
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mov $_pa(initial_page_table), %eax
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mov %eax, %cr3
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mov %cr0, %eax
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or $(X86_CR0_PG | X86_CR0_PE), %eax
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mov %eax, %cr0
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ljmp $PVH_CS_SEL, $1f
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1:
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call xen_prepare_pvh
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mov $_pa(pvh_bootparams), %esi
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/* startup_32 doesn't expect paging and PAE to be on. */
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ljmp $PVH_CS_SEL, $_pa(2f)
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2:
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mov %cr0, %eax
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and $~X86_CR0_PG, %eax
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mov %eax, %cr0
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mov %cr4, %eax
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and $~X86_CR4_PAE, %eax
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mov %eax, %cr4
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ljmp $PVH_CS_SEL, $_pa(startup_32)
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#endif
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SYM_CODE_END(pvh_start_xen)
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.section ".init.data","aw"
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.balign 8
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SYM_DATA_START_LOCAL(gdt)
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.word gdt_end - gdt_start
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.long _pa(gdt_start)
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.word 0
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SYM_DATA_END(gdt)
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SYM_DATA_START_LOCAL(gdt_start)
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.quad 0x0000000000000000 /* NULL descriptor */
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#ifdef CONFIG_X86_64
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.quad GDT_ENTRY(0xa09a, 0, 0xfffff) /* PVH_CS_SEL */
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#else
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.quad GDT_ENTRY(0xc09a, 0, 0xfffff) /* PVH_CS_SEL */
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#endif
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.quad GDT_ENTRY(0xc092, 0, 0xfffff) /* PVH_DS_SEL */
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SYM_DATA_END_LABEL(gdt_start, SYM_L_LOCAL, gdt_end)
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.balign 16
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SYM_DATA_LOCAL(canary, .fill 48, 1, 0)
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SYM_DATA_START_LOCAL(early_stack)
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.fill BOOT_STACK_SIZE, 1, 0
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SYM_DATA_END_LABEL(early_stack, SYM_L_LOCAL, early_stack_end)
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ELFNOTE(Xen, XEN_ELFNOTE_PHYS32_ENTRY,
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_ASM_PTR (pvh_start_xen - __START_KERNEL_map))
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