b87d390196
As with EU masks, it's easier to store subslice/DSS masks internally in a format that's more natural for the driver to work with, and then only covert into the u8[] uapi form when the query ioctl is invoked. Since the hardware design changed significantly with Xe_HP, we'll use a union to choose between the old "hsw-style" subslice masks or the newer xehp mask. HSW-style masks will be stored in an array of u8's, indexed by slice (there's never more than 6 subslices per slice on older platforms). For Xe_HP and beyond where slices no longer exist, we only need a single bitmask. However we already know that this mask is eventually going to grow too large for a simple u64 to hold, so we'll represent it in a manner that can be operated on by the utilities in linux/bitmap.h. v2: - Fix typo: BIT(s) -> BIT(ss) in gen9_sseu_device_status() v3: - Eliminate sseu->ss_stride and just calculate the stride while specifically handling uapi. (Tvrtko) - Use BITMAP_BITS() macro to refer to size of masks rather than passing I915_MAX_SS_FUSE_BITS directly. (Tvrtko) - Report compute/geometry DSS masks separately when dumping Xe_HP SSEU info. (Tvrtko) - Restore dropped range checks to intel_sseu_has_subslice(). (Tvrtko) v4: - Make the bitmap size macro check the size of the .xehp field rather than the containing union. (Tvrtko) - Don't add GEM_BUG_ON() intel_sseu_has_subslice()'s check for whether slice or subslice ID exceed sseu->max_[sub]slices; various loops in the driver are expected to exceed these, so we should just silently return 'false.' v5: - Move XEHP_BITMAP_BITS() to the header so that we can also replace a usage of I915_MAX_SS_FUSE_BITS in one of the inline functions. (Bala) - Change the local variable in intel_slicemask_from_xehp_dssmask() from u16 to 'unsigned long' to make it a bit more future-proof. Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220601150725.521468-6-matthew.d.roper@intel.com
300 lines
8.2 KiB
C
300 lines
8.2 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2020 Intel Corporation
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*/
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#include <linux/bitmap.h>
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#include <linux/string_helpers.h>
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#include "i915_drv.h"
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#include "intel_gt_debugfs.h"
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#include "intel_gt_regs.h"
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#include "intel_sseu_debugfs.h"
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static void cherryview_sseu_device_status(struct intel_gt *gt,
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struct sseu_dev_info *sseu)
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{
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#define SS_MAX 2
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struct intel_uncore *uncore = gt->uncore;
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const int ss_max = SS_MAX;
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u32 sig1[SS_MAX], sig2[SS_MAX];
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int ss;
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sig1[0] = intel_uncore_read(uncore, CHV_POWER_SS0_SIG1);
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sig1[1] = intel_uncore_read(uncore, CHV_POWER_SS1_SIG1);
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sig2[0] = intel_uncore_read(uncore, CHV_POWER_SS0_SIG2);
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sig2[1] = intel_uncore_read(uncore, CHV_POWER_SS1_SIG2);
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for (ss = 0; ss < ss_max; ss++) {
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unsigned int eu_cnt;
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if (sig1[ss] & CHV_SS_PG_ENABLE)
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/* skip disabled subslice */
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continue;
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sseu->slice_mask = BIT(0);
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sseu->subslice_mask.hsw[0] |= BIT(ss);
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eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
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((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
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((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
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((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
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sseu->eu_total += eu_cnt;
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sseu->eu_per_subslice = max_t(unsigned int,
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sseu->eu_per_subslice, eu_cnt);
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}
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#undef SS_MAX
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}
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static void gen11_sseu_device_status(struct intel_gt *gt,
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struct sseu_dev_info *sseu)
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{
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#define SS_MAX 8
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struct intel_uncore *uncore = gt->uncore;
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const struct intel_gt_info *info = >->info;
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u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2];
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int s, ss;
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for (s = 0; s < info->sseu.max_slices; s++) {
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/*
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* FIXME: Valid SS Mask respects the spec and read
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* only valid bits for those registers, excluding reserved
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* although this seems wrong because it would leave many
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* subslices without ACK.
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*/
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s_reg[s] = intel_uncore_read(uncore, GEN10_SLICE_PGCTL_ACK(s)) &
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GEN10_PGCTL_VALID_SS_MASK(s);
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eu_reg[2 * s] = intel_uncore_read(uncore,
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GEN10_SS01_EU_PGCTL_ACK(s));
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eu_reg[2 * s + 1] = intel_uncore_read(uncore,
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GEN10_SS23_EU_PGCTL_ACK(s));
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}
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eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
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GEN9_PGCTL_SSA_EU19_ACK |
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GEN9_PGCTL_SSA_EU210_ACK |
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GEN9_PGCTL_SSA_EU311_ACK;
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eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
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GEN9_PGCTL_SSB_EU19_ACK |
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GEN9_PGCTL_SSB_EU210_ACK |
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GEN9_PGCTL_SSB_EU311_ACK;
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for (s = 0; s < info->sseu.max_slices; s++) {
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if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
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/* skip disabled slice */
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continue;
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sseu->slice_mask |= BIT(s);
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sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
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for (ss = 0; ss < info->sseu.max_subslices; ss++) {
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unsigned int eu_cnt;
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if (info->sseu.has_subslice_pg &&
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!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
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/* skip disabled subslice */
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continue;
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eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] &
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eu_mask[ss % 2]);
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sseu->eu_total += eu_cnt;
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sseu->eu_per_subslice = max_t(unsigned int,
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sseu->eu_per_subslice,
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eu_cnt);
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}
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}
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#undef SS_MAX
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}
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static void gen9_sseu_device_status(struct intel_gt *gt,
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struct sseu_dev_info *sseu)
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{
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#define SS_MAX 3
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struct intel_uncore *uncore = gt->uncore;
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const struct intel_gt_info *info = >->info;
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u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2];
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int s, ss;
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for (s = 0; s < info->sseu.max_slices; s++) {
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s_reg[s] = intel_uncore_read(uncore, GEN9_SLICE_PGCTL_ACK(s));
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eu_reg[2 * s] =
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intel_uncore_read(uncore, GEN9_SS01_EU_PGCTL_ACK(s));
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eu_reg[2 * s + 1] =
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intel_uncore_read(uncore, GEN9_SS23_EU_PGCTL_ACK(s));
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}
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eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
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GEN9_PGCTL_SSA_EU19_ACK |
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GEN9_PGCTL_SSA_EU210_ACK |
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GEN9_PGCTL_SSA_EU311_ACK;
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eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
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GEN9_PGCTL_SSB_EU19_ACK |
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GEN9_PGCTL_SSB_EU210_ACK |
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GEN9_PGCTL_SSB_EU311_ACK;
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for (s = 0; s < info->sseu.max_slices; s++) {
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if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
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/* skip disabled slice */
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continue;
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sseu->slice_mask |= BIT(s);
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if (IS_GEN9_BC(gt->i915))
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sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
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for (ss = 0; ss < info->sseu.max_subslices; ss++) {
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unsigned int eu_cnt;
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if (IS_GEN9_LP(gt->i915)) {
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if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
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/* skip disabled subslice */
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continue;
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sseu->subslice_mask.hsw[s] |= BIT(ss);
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}
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eu_cnt = eu_reg[2 * s + ss / 2] & eu_mask[ss % 2];
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eu_cnt = 2 * hweight32(eu_cnt);
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sseu->eu_total += eu_cnt;
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sseu->eu_per_subslice = max_t(unsigned int,
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sseu->eu_per_subslice,
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eu_cnt);
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}
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}
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#undef SS_MAX
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}
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static void bdw_sseu_device_status(struct intel_gt *gt,
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struct sseu_dev_info *sseu)
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{
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const struct intel_gt_info *info = >->info;
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u32 slice_info = intel_uncore_read(gt->uncore, GEN8_GT_SLICE_INFO);
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int s;
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sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
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if (sseu->slice_mask) {
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sseu->eu_per_subslice = info->sseu.eu_per_subslice;
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for (s = 0; s < fls(sseu->slice_mask); s++)
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sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
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sseu->eu_total = sseu->eu_per_subslice *
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intel_sseu_subslice_total(sseu);
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/* subtract fused off EU(s) from enabled slice(s) */
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for (s = 0; s < fls(sseu->slice_mask); s++) {
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u8 subslice_7eu = info->sseu.subslice_7eu[s];
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sseu->eu_total -= hweight8(subslice_7eu);
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}
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}
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}
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static void i915_print_sseu_info(struct seq_file *m,
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bool is_available_info,
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bool has_pooled_eu,
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const struct sseu_dev_info *sseu)
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{
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const char *type = is_available_info ? "Available" : "Enabled";
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seq_printf(m, " %s Slice Mask: %04x\n", type,
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sseu->slice_mask);
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seq_printf(m, " %s Slice Total: %u\n", type,
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hweight8(sseu->slice_mask));
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seq_printf(m, " %s Subslice Total: %u\n", type,
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intel_sseu_subslice_total(sseu));
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intel_sseu_print_ss_info(type, sseu, m);
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seq_printf(m, " %s EU Total: %u\n", type,
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sseu->eu_total);
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seq_printf(m, " %s EU Per Subslice: %u\n", type,
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sseu->eu_per_subslice);
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if (!is_available_info)
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return;
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seq_printf(m, " Has Pooled EU: %s\n", str_yes_no(has_pooled_eu));
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if (has_pooled_eu)
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seq_printf(m, " Min EU in pool: %u\n", sseu->min_eu_in_pool);
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seq_printf(m, " Has Slice Power Gating: %s\n",
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str_yes_no(sseu->has_slice_pg));
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seq_printf(m, " Has Subslice Power Gating: %s\n",
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str_yes_no(sseu->has_subslice_pg));
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seq_printf(m, " Has EU Power Gating: %s\n",
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str_yes_no(sseu->has_eu_pg));
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}
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/*
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* this is called from top-level debugfs as well, so we can't get the gt from
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* the seq_file.
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*/
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int intel_sseu_status(struct seq_file *m, struct intel_gt *gt)
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{
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struct drm_i915_private *i915 = gt->i915;
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const struct intel_gt_info *info = >->info;
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struct sseu_dev_info *sseu;
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intel_wakeref_t wakeref;
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if (GRAPHICS_VER(i915) < 8)
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return -ENODEV;
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seq_puts(m, "SSEU Device Info\n");
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i915_print_sseu_info(m, true, HAS_POOLED_EU(i915), &info->sseu);
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seq_puts(m, "SSEU Device Status\n");
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sseu = kzalloc(sizeof(*sseu), GFP_KERNEL);
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if (!sseu)
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return -ENOMEM;
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intel_sseu_set_info(sseu, info->sseu.max_slices,
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info->sseu.max_subslices,
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info->sseu.max_eus_per_subslice);
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with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
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if (IS_CHERRYVIEW(i915))
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cherryview_sseu_device_status(gt, sseu);
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else if (IS_BROADWELL(i915))
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bdw_sseu_device_status(gt, sseu);
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else if (GRAPHICS_VER(i915) == 9)
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gen9_sseu_device_status(gt, sseu);
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else if (GRAPHICS_VER(i915) >= 11)
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gen11_sseu_device_status(gt, sseu);
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}
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i915_print_sseu_info(m, false, HAS_POOLED_EU(i915), sseu);
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kfree(sseu);
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return 0;
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}
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static int sseu_status_show(struct seq_file *m, void *unused)
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{
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struct intel_gt *gt = m->private;
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return intel_sseu_status(m, gt);
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}
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DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(sseu_status);
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static int sseu_topology_show(struct seq_file *m, void *unused)
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{
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struct intel_gt *gt = m->private;
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struct drm_printer p = drm_seq_file_printer(m);
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intel_sseu_print_topology(gt->i915, >->info.sseu, &p);
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return 0;
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}
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DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(sseu_topology);
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void intel_sseu_debugfs_register(struct intel_gt *gt, struct dentry *root)
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{
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static const struct intel_gt_debugfs_file files[] = {
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{ "sseu_status", &sseu_status_fops, NULL },
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{ "sseu_topology", &sseu_topology_fops, NULL },
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};
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intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);
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}
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