62183863f7
After enabling CONFIG_REGULATOR_DEBUG=y we observer below debug logs.
Changes help link VDDCP_A and VDDCPU_B pwm regulator to 12V regulator
supply instead of dummy regulator.
[ 4.147196] VDDCPU_A: will resolve supply early: pwm
[ 4.147216] pwm-regulator regulator-vddcpu-a: Looking up pwm-supply from device tree
[ 4.147227] pwm-regulator regulator-vddcpu-a: Looking up pwm-supply property in node /regulator-vddcpu-a failed
[ 4.147258] VDDCPU_A: supplied by regulator-dummy
[ 4.147288] regulator-dummy: could not add device link regulator.12: -ENOENT
[ 4.147353] VDDCPU_A: 721 <--> 1022 mV at 871 mV, enabled
[ 4.152014] VDDCPU_B: will resolve supply early: pwm
[ 4.152035] pwm-regulator regulator-vddcpu-b: Looking up pwm-supply from device tree
[ 4.152047] pwm-regulator regulator-vddcpu-b: Looking up pwm-supply property in node /regulator-vddcpu-b failed
[ 4.152079] VDDCPU_B: supplied by regulator-dummy
[ 4.152108] regulator-dummy: could not add device link regulator.13: -ENOENT
Fixes: c6d29c66e582 ("arm64: dts: meson-g12b-khadas-vim3: add initial device-tree")
Fixes: d14734a04a8a ("arm64: dts: meson-g12b-odroid-n2: enable DVFS")
Fixes: 3cb74db9b256 ("arm64: dts: meson: convert ugoos-am6 to common w400 dtsi")
Cc: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/20210919202918.3556-3-linux.amoon@gmail.com
108 lines
2.0 KiB
Plaintext
108 lines
2.0 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2019 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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* Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
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*/
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/ {
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model = "Khadas VIM3";
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vddcpu_a: regulator-vddcpu-a {
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/*
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* MP8756GD Regulator.
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*/
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compatible = "pwm-regulator";
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regulator-name = "VDDCPU_A";
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regulator-min-microvolt = <690000>;
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regulator-max-microvolt = <1050000>;
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pwm-supply = <&dc_in>;
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pwms = <&pwm_ab 0 1250 0>;
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pwm-dutycycle-range = <100 0>;
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regulator-boot-on;
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regulator-always-on;
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};
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vddcpu_b: regulator-vddcpu-b {
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/*
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* Silergy SY8030DEC Regulator.
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*/
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compatible = "pwm-regulator";
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regulator-name = "VDDCPU_B";
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regulator-min-microvolt = <690000>;
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regulator-max-microvolt = <1050000>;
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pwm-supply = <&vsys_3v3>;
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pwms = <&pwm_AO_cd 1 1250 0>;
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pwm-dutycycle-range = <100 0>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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&cpu0 {
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cpu-supply = <&vddcpu_b>;
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operating-points-v2 = <&cpu_opp_table_0>;
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clocks = <&clkc CLKID_CPU_CLK>;
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clock-latency = <50000>;
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};
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&cpu1 {
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cpu-supply = <&vddcpu_b>;
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operating-points-v2 = <&cpu_opp_table_0>;
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clocks = <&clkc CLKID_CPU_CLK>;
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clock-latency = <50000>;
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};
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&cpu100 {
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cpu-supply = <&vddcpu_a>;
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operating-points-v2 = <&cpub_opp_table_1>;
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clocks = <&clkc CLKID_CPUB_CLK>;
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clock-latency = <50000>;
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};
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&cpu101 {
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cpu-supply = <&vddcpu_a>;
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operating-points-v2 = <&cpub_opp_table_1>;
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clocks = <&clkc CLKID_CPUB_CLK>;
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clock-latency = <50000>;
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};
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&cpu102 {
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cpu-supply = <&vddcpu_a>;
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operating-points-v2 = <&cpub_opp_table_1>;
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clocks = <&clkc CLKID_CPUB_CLK>;
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clock-latency = <50000>;
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};
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&cpu103 {
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cpu-supply = <&vddcpu_a>;
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operating-points-v2 = <&cpub_opp_table_1>;
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clocks = <&clkc CLKID_CPUB_CLK>;
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clock-latency = <50000>;
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};
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&pwm_ab {
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pinctrl-0 = <&pwm_a_e_pins>;
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pinctrl-names = "default";
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clocks = <&xtal>;
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clock-names = "clkin0";
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status = "okay";
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};
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&pwm_AO_cd {
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pinctrl-0 = <&pwm_ao_d_e_pins>;
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pinctrl-names = "default";
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clocks = <&xtal>;
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clock-names = "clkin1";
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status = "okay";
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};
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