- Use common KVM implementation of MMU memory caches - SBI v0.2 support for Guest - Initial KVM selftests support - Fix to avoid spurious virtual interrupts after clearing hideleg CSR - Update email address for Anup and Atish ARM: - Simplification of the 'vcpu first run' by integrating it into KVM's 'pid change' flow - Refactoring of the FP and SVE state tracking, also leading to a simpler state and less shared data between EL1 and EL2 in the nVHE case - Tidy up the header file usage for the nvhe hyp object - New HYP unsharing mechanism, finally allowing pages to be unmapped from the Stage-1 EL2 page-tables - Various pKVM cleanups around refcounting and sharing - A couple of vgic fixes for bugs that would trigger once the vcpu xarray rework is merged, but not sooner - Add minimal support for ARMv8.7's PMU extension - Rework kvm_pgtable initialisation ahead of the NV work - New selftest for IRQ injection - Teach selftests about the lack of default IPA space and page sizes - Expand sysreg selftest to deal with Pointer Authentication - The usual bunch of cleanups and doc update s390: - fix sigp sense/start/stop/inconsistency - cleanups x86: - Clean up some function prototypes more - improved gfn_to_pfn_cache with proper invalidation, used by Xen emulation - add KVM_IRQ_ROUTING_XEN_EVTCHN and event channel delivery - completely remove potential TOC/TOU races in nested SVM consistency checks - update some PMCs on emulated instructions - Intel AMX support (joint work between Thomas and Intel) - large MMU cleanups - module parameter to disable PMU virtualization - cleanup register cache - first part of halt handling cleanups - Hyper-V enlightened MSR bitmap support for nested hypervisors Generic: - clean up Makefiles - introduce CONFIG_HAVE_KVM_DIRTY_RING - optimize memslot lookup using a tree - optimize vCPU array usage by converting to xarray -----BEGIN PGP SIGNATURE----- iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmHhxvsUHHBib256aW5p QHJlZGhhdC5jb20ACgkQv/vSX3jHroPZkAf+Nz92UL/5nNGcdHtE4m7AToMmitE9 bYkesf9BMQvAe5wjkABLuoHGi6ay4jabo4fiGzbdkiK7lO5YgfsWiMB3/MT5fl4E jRPzaVQabp3YZLM8UYCBmfUVuRj524S967SfSRe0AvYjDEH8y7klPf4+7sCsFT0/ Px9Vf2KGuOlf0eM78yKg4rGaF0jS22eLgXm6FfNMY8/e29ZAo/jyUmqBY+Z2xxZG aWhceDtSheW1jwLHLj3nOlQJvHTn8LVGXBE/R8Gda3ZjrBV2rKaDi4Fh+HD+dz86 2zVXwzQ7uck2CMW73GMoXMTWoKSHMyvlBOs1BdvBm4UsnGcXR+q8IFCeuQ== =s73m -----END PGP SIGNATURE----- Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm Pull kvm updates from Paolo Bonzini: "RISCV: - Use common KVM implementation of MMU memory caches - SBI v0.2 support for Guest - Initial KVM selftests support - Fix to avoid spurious virtual interrupts after clearing hideleg CSR - Update email address for Anup and Atish ARM: - Simplification of the 'vcpu first run' by integrating it into KVM's 'pid change' flow - Refactoring of the FP and SVE state tracking, also leading to a simpler state and less shared data between EL1 and EL2 in the nVHE case - Tidy up the header file usage for the nvhe hyp object - New HYP unsharing mechanism, finally allowing pages to be unmapped from the Stage-1 EL2 page-tables - Various pKVM cleanups around refcounting and sharing - A couple of vgic fixes for bugs that would trigger once the vcpu xarray rework is merged, but not sooner - Add minimal support for ARMv8.7's PMU extension - Rework kvm_pgtable initialisation ahead of the NV work - New selftest for IRQ injection - Teach selftests about the lack of default IPA space and page sizes - Expand sysreg selftest to deal with Pointer Authentication - The usual bunch of cleanups and doc update s390: - fix sigp sense/start/stop/inconsistency - cleanups x86: - Clean up some function prototypes more - improved gfn_to_pfn_cache with proper invalidation, used by Xen emulation - add KVM_IRQ_ROUTING_XEN_EVTCHN and event channel delivery - completely remove potential TOC/TOU races in nested SVM consistency checks - update some PMCs on emulated instructions - Intel AMX support (joint work between Thomas and Intel) - large MMU cleanups - module parameter to disable PMU virtualization - cleanup register cache - first part of halt handling cleanups - Hyper-V enlightened MSR bitmap support for nested hypervisors Generic: - clean up Makefiles - introduce CONFIG_HAVE_KVM_DIRTY_RING - optimize memslot lookup using a tree - optimize vCPU array usage by converting to xarray" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (268 commits) x86/fpu: Fix inline prefix warnings selftest: kvm: Add amx selftest selftest: kvm: Move struct kvm_x86_state to header selftest: kvm: Reorder vcpu_load_state steps for AMX kvm: x86: Disable interception for IA32_XFD on demand x86/fpu: Provide fpu_sync_guest_vmexit_xfd_state() kvm: selftests: Add support for KVM_CAP_XSAVE2 kvm: x86: Add support for getting/setting expanded xstate buffer x86/fpu: Add uabi_size to guest_fpu kvm: x86: Add CPUID support for Intel AMX kvm: x86: Add XCR0 support for Intel AMX kvm: x86: Disable RDMSR interception of IA32_XFD_ERR kvm: x86: Emulate IA32_XFD_ERR for guest kvm: x86: Intercept #NM for saving IA32_XFD_ERR x86/fpu: Prepare xfd_err in struct fpu_guest kvm: x86: Add emulation for IA32_XFD x86/fpu: Provide fpu_update_guest_xfd() for IA32_XFD emulation kvm: x86: Enable dynamic xfeatures at KVM_SET_CPUID2 x86/fpu: Provide fpu_enable_guest_xfd_features() for KVM x86/fpu: Add guest support to xfd_enable_feature() ...
348 lines
9.6 KiB
C
348 lines
9.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __KVM_X86_VMX_INSN_H
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#define __KVM_X86_VMX_INSN_H
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#include <linux/nospec.h>
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#include <asm/vmx.h>
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#include "evmcs.h"
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#include "vmcs.h"
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#include "x86.h"
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asmlinkage void vmread_error(unsigned long field, bool fault);
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__attribute__((regparm(0))) void vmread_error_trampoline(unsigned long field,
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bool fault);
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void vmwrite_error(unsigned long field, unsigned long value);
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void vmclear_error(struct vmcs *vmcs, u64 phys_addr);
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void vmptrld_error(struct vmcs *vmcs, u64 phys_addr);
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void invvpid_error(unsigned long ext, u16 vpid, gva_t gva);
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void invept_error(unsigned long ext, u64 eptp, gpa_t gpa);
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static __always_inline void vmcs_check16(unsigned long field)
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{
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BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
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"16-bit accessor invalid for 64-bit field");
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BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
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"16-bit accessor invalid for 64-bit high field");
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BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
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"16-bit accessor invalid for 32-bit high field");
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BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
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"16-bit accessor invalid for natural width field");
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}
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static __always_inline void vmcs_check32(unsigned long field)
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{
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BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
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"32-bit accessor invalid for 16-bit field");
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BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
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"32-bit accessor invalid for 64-bit field");
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BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
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"32-bit accessor invalid for 64-bit high field");
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BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
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"32-bit accessor invalid for natural width field");
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}
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static __always_inline void vmcs_check64(unsigned long field)
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{
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BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
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"64-bit accessor invalid for 16-bit field");
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BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
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"64-bit accessor invalid for 64-bit high field");
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BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
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"64-bit accessor invalid for 32-bit field");
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BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
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"64-bit accessor invalid for natural width field");
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}
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static __always_inline void vmcs_checkl(unsigned long field)
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{
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BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
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"Natural width accessor invalid for 16-bit field");
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BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
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"Natural width accessor invalid for 64-bit field");
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BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
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"Natural width accessor invalid for 64-bit high field");
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BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
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"Natural width accessor invalid for 32-bit field");
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}
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static __always_inline unsigned long __vmcs_readl(unsigned long field)
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{
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unsigned long value;
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#ifdef CONFIG_CC_HAS_ASM_GOTO_OUTPUT
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asm_volatile_goto("1: vmread %[field], %[output]\n\t"
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"jna %l[do_fail]\n\t"
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_ASM_EXTABLE(1b, %l[do_exception])
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: [output] "=r" (value)
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: [field] "r" (field)
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: "cc"
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: do_fail, do_exception);
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return value;
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do_fail:
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WARN_ONCE(1, "kvm: vmread failed: field=%lx\n", field);
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pr_warn_ratelimited("kvm: vmread failed: field=%lx\n", field);
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return 0;
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do_exception:
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kvm_spurious_fault();
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return 0;
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#else /* !CONFIG_CC_HAS_ASM_GOTO_OUTPUT */
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asm volatile("1: vmread %2, %1\n\t"
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".byte 0x3e\n\t" /* branch taken hint */
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"ja 3f\n\t"
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/*
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* VMREAD failed. Push '0' for @fault, push the failing
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* @field, and bounce through the trampoline to preserve
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* volatile registers.
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*/
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"xorl %k1, %k1\n\t"
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"2:\n\t"
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"push %1\n\t"
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"push %2\n\t"
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"call vmread_error_trampoline\n\t"
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/*
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* Unwind the stack. Note, the trampoline zeros out the
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* memory for @fault so that the result is '0' on error.
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*/
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"pop %2\n\t"
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"pop %1\n\t"
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"3:\n\t"
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/* VMREAD faulted. As above, except push '1' for @fault. */
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_ASM_EXTABLE_TYPE_REG(1b, 2b, EX_TYPE_ONE_REG, %1)
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: ASM_CALL_CONSTRAINT, "=&r"(value) : "r"(field) : "cc");
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return value;
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#endif /* CONFIG_CC_HAS_ASM_GOTO_OUTPUT */
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}
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static __always_inline u16 vmcs_read16(unsigned long field)
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{
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vmcs_check16(field);
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if (static_branch_unlikely(&enable_evmcs))
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return evmcs_read16(field);
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return __vmcs_readl(field);
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}
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static __always_inline u32 vmcs_read32(unsigned long field)
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{
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vmcs_check32(field);
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if (static_branch_unlikely(&enable_evmcs))
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return evmcs_read32(field);
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return __vmcs_readl(field);
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}
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static __always_inline u64 vmcs_read64(unsigned long field)
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{
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vmcs_check64(field);
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if (static_branch_unlikely(&enable_evmcs))
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return evmcs_read64(field);
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#ifdef CONFIG_X86_64
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return __vmcs_readl(field);
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#else
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return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
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#endif
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}
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static __always_inline unsigned long vmcs_readl(unsigned long field)
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{
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vmcs_checkl(field);
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if (static_branch_unlikely(&enable_evmcs))
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return evmcs_read64(field);
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return __vmcs_readl(field);
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}
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#define vmx_asm1(insn, op1, error_args...) \
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do { \
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asm_volatile_goto("1: " __stringify(insn) " %0\n\t" \
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".byte 0x2e\n\t" /* branch not taken hint */ \
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"jna %l[error]\n\t" \
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_ASM_EXTABLE(1b, %l[fault]) \
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: : op1 : "cc" : error, fault); \
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return; \
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error: \
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instrumentation_begin(); \
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insn##_error(error_args); \
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instrumentation_end(); \
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return; \
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fault: \
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kvm_spurious_fault(); \
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} while (0)
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#define vmx_asm2(insn, op1, op2, error_args...) \
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do { \
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asm_volatile_goto("1: " __stringify(insn) " %1, %0\n\t" \
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".byte 0x2e\n\t" /* branch not taken hint */ \
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"jna %l[error]\n\t" \
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_ASM_EXTABLE(1b, %l[fault]) \
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: : op1, op2 : "cc" : error, fault); \
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return; \
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error: \
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instrumentation_begin(); \
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insn##_error(error_args); \
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instrumentation_end(); \
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return; \
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fault: \
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kvm_spurious_fault(); \
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} while (0)
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static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
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{
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vmx_asm2(vmwrite, "r"(field), "rm"(value), field, value);
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}
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static __always_inline void vmcs_write16(unsigned long field, u16 value)
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{
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vmcs_check16(field);
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if (static_branch_unlikely(&enable_evmcs))
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return evmcs_write16(field, value);
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__vmcs_writel(field, value);
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}
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static __always_inline void vmcs_write32(unsigned long field, u32 value)
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{
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vmcs_check32(field);
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if (static_branch_unlikely(&enable_evmcs))
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return evmcs_write32(field, value);
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__vmcs_writel(field, value);
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}
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static __always_inline void vmcs_write64(unsigned long field, u64 value)
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{
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vmcs_check64(field);
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if (static_branch_unlikely(&enable_evmcs))
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return evmcs_write64(field, value);
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__vmcs_writel(field, value);
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#ifndef CONFIG_X86_64
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__vmcs_writel(field+1, value >> 32);
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#endif
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}
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static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
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{
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vmcs_checkl(field);
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if (static_branch_unlikely(&enable_evmcs))
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return evmcs_write64(field, value);
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__vmcs_writel(field, value);
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}
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static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
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{
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BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
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"vmcs_clear_bits does not support 64-bit fields");
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if (static_branch_unlikely(&enable_evmcs))
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return evmcs_write32(field, evmcs_read32(field) & ~mask);
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__vmcs_writel(field, __vmcs_readl(field) & ~mask);
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}
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static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
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{
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BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
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"vmcs_set_bits does not support 64-bit fields");
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if (static_branch_unlikely(&enable_evmcs))
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return evmcs_write32(field, evmcs_read32(field) | mask);
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__vmcs_writel(field, __vmcs_readl(field) | mask);
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}
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static inline void vmcs_clear(struct vmcs *vmcs)
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{
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u64 phys_addr = __pa(vmcs);
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vmx_asm1(vmclear, "m"(phys_addr), vmcs, phys_addr);
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}
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static inline void vmcs_load(struct vmcs *vmcs)
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{
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u64 phys_addr = __pa(vmcs);
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if (static_branch_unlikely(&enable_evmcs))
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return evmcs_load(phys_addr);
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vmx_asm1(vmptrld, "m"(phys_addr), vmcs, phys_addr);
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}
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static inline void __invvpid(unsigned long ext, u16 vpid, gva_t gva)
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{
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struct {
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u64 vpid : 16;
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u64 rsvd : 48;
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u64 gva;
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} operand = { vpid, 0, gva };
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vmx_asm2(invvpid, "r"(ext), "m"(operand), ext, vpid, gva);
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}
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static inline void __invept(unsigned long ext, u64 eptp, gpa_t gpa)
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{
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struct {
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u64 eptp, gpa;
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} operand = {eptp, gpa};
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vmx_asm2(invept, "r"(ext), "m"(operand), ext, eptp, gpa);
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}
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static inline void vpid_sync_vcpu_single(int vpid)
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{
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if (vpid == 0)
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return;
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__invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
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}
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static inline void vpid_sync_vcpu_global(void)
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{
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__invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
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}
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static inline void vpid_sync_context(int vpid)
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{
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if (cpu_has_vmx_invvpid_single())
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vpid_sync_vcpu_single(vpid);
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else if (vpid != 0)
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vpid_sync_vcpu_global();
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}
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static inline void vpid_sync_vcpu_addr(int vpid, gva_t addr)
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{
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if (vpid == 0)
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return;
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if (cpu_has_vmx_invvpid_individual_addr())
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__invvpid(VMX_VPID_EXTENT_INDIVIDUAL_ADDR, vpid, addr);
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else
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vpid_sync_context(vpid);
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}
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static inline void ept_sync_global(void)
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{
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__invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
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}
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static inline void ept_sync_context(u64 eptp)
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{
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if (cpu_has_vmx_invept_context())
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__invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
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else
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ept_sync_global();
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}
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#endif /* __KVM_X86_VMX_INSN_H */
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