95015be8f4
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
94 lines
3.2 KiB
C
94 lines
3.2 KiB
C
/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DISPLAY_CLOCK_INTERFACE_H__
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#define __DISPLAY_CLOCK_INTERFACE_H__
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#include "hw_sequencer_types.h"
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#include "grph_object_defs.h"
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#include "signal_types.h"
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/* Enumeration of all clocks states */
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enum clocks_state {
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CLOCKS_STATE_INVALID = 0,
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CLOCKS_STATE_ULTRA_LOW,
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CLOCKS_STATE_LOW,
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CLOCKS_STATE_NOMINAL,
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CLOCKS_STATE_PERFORMANCE,
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/* Starting from DCE11, Max 8 level DPM state supported */
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CLOCKS_DPM_STATE_LEVEL_INVALID = CLOCKS_STATE_INVALID,
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CLOCKS_DPM_STATE_LEVEL_0 = CLOCKS_STATE_ULTRA_LOW,
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CLOCKS_DPM_STATE_LEVEL_1 = CLOCKS_STATE_LOW,
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CLOCKS_DPM_STATE_LEVEL_2 = CLOCKS_STATE_NOMINAL,
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CLOCKS_DPM_STATE_LEVEL_3 = CLOCKS_STATE_PERFORMANCE,
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CLOCKS_DPM_STATE_LEVEL_4 = CLOCKS_DPM_STATE_LEVEL_3 + 1,
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CLOCKS_DPM_STATE_LEVEL_5 = CLOCKS_DPM_STATE_LEVEL_4 + 1,
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CLOCKS_DPM_STATE_LEVEL_6 = CLOCKS_DPM_STATE_LEVEL_5 + 1,
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CLOCKS_DPM_STATE_LEVEL_7 = CLOCKS_DPM_STATE_LEVEL_6 + 1,
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};
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/* Structure containing all state-dependent clocks
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* (dependent on "enum clocks_state") */
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struct state_dependent_clocks {
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uint32_t display_clk_khz;
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uint32_t pixel_clk_khz;
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};
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struct display_clock {
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struct dc_context *ctx;
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const struct display_clock_funcs *funcs;
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uint32_t min_display_clk_threshold_khz;
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/* Max display block clocks state*/
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enum clocks_state max_clks_state;
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enum clocks_state cur_min_clks_state;
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};
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struct display_clock_funcs {
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void (*destroy)(struct display_clock **to_destroy);
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void (*set_clock)(struct display_clock *disp_clk,
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uint32_t requested_clock_khz);
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enum clocks_state (*get_required_clocks_state)(
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struct display_clock *disp_clk,
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struct state_dependent_clocks *req_clocks);
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bool (*set_min_clocks_state)(struct display_clock *disp_clk,
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enum clocks_state clocks_state);
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uint32_t (*get_dp_ref_clk_frequency)(struct display_clock *disp_clk);
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};
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struct display_clock *dal_display_clock_dce112_create(
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struct dc_context *ctx);
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struct display_clock *dal_display_clock_dce110_create(
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struct dc_context *ctx);
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struct display_clock *dal_display_clock_dce80_create(
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struct dc_context *ctx);
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void dal_display_clock_destroy(struct display_clock **to_destroy);
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#endif /* __DISPLAY_CLOCK_INTERFACE_H__ */
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