d39fb17276
Add a driver to support the PLLs in PolarFire SoC's Clock Conditioning Circuitry, an instance of which is located in each ordinal corner of the FPGA. Only get_rate() is supported as these clocks are intended to be statically configured by the FPGA design. Currently, the DLLs are not supported by this driver. For more information on the hardware, see "PolarFire SoC FPGA Clocking Resources" in the link below. Link: https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220908143651.1252601-5-conor.dooley@microchip.com |
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| .. | ||
| clk-core.c | ||
| clk-core.h | ||
| clk-mpfs-ccc.c | ||
| clk-mpfs.c | ||
| clk-pic32mzda.c | ||
| Kconfig | ||
| Makefile | ||