3cec368a8b
DSA switches can fall into one of two categories: switches where all ports follow standard '(ethernet-)?port' properties, and switches that have additional properties for the ports. The scenario where DSA ports are all standardized can be handled by switches with a reference to the new 'dsa.yaml#/$defs/ethernet-ports'. The scenario where DSA ports require additional properties can reference '$dsa.yaml#' directly. This will allow switches to reference these standard definitions of the DSA switch, but add additional properties under the port nodes. Suggested-by: Rob Herring <robh@kernel.org> Signed-off-by: Colin Foster <colin.foster@in-advantage.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Alvin Šipraga <alsi@bang-olufsen.dk> # realtek Acked-by: Arınç ÜNAL <arinc.unal@arinc9.com> Signed-off-by: David S. Miller <davem@davemloft.net>
193 lines
5.8 KiB
YAML
193 lines
5.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/dsa/microchip,lan937x.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: LAN937x Ethernet Switch Series
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maintainers:
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- UNGLinuxDriver@microchip.com
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allOf:
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- $ref: dsa.yaml#/$defs/ethernet-ports
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properties:
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compatible:
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enum:
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- microchip,lan9370
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- microchip,lan9371
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- microchip,lan9372
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- microchip,lan9373
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- microchip,lan9374
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reg:
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maxItems: 1
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spi-max-frequency:
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maximum: 50000000
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reset-gpios:
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description: Optional gpio specifier for a reset line
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maxItems: 1
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mdio:
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$ref: /schemas/net/mdio.yaml#
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unevaluatedProperties: false
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patternProperties:
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"^(ethernet-)?ports$":
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patternProperties:
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"^(ethernet-)?port@[0-9]+$":
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allOf:
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- if:
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properties:
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phy-mode:
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contains:
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enum:
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- rgmii
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- rgmii-id
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- rgmii-txid
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- rgmii-rxid
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then:
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properties:
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rx-internal-delay-ps:
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enum: [0, 2000]
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default: 0
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tx-internal-delay-ps:
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enum: [0, 2000]
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default: 0
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required:
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- compatible
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- reg
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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macb0 {
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#address-cells = <1>;
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#size-cells = <0>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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spi {
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#address-cells = <1>;
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#size-cells = <0>;
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lan9374: switch@0 {
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compatible = "microchip,lan9374";
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reg = <0>;
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spi-max-frequency = <44000000>;
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan1";
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phy-mode = "internal";
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phy-handle = <&t1phy0>;
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};
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port@1 {
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reg = <1>;
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label = "lan2";
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phy-mode = "internal";
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phy-handle = <&t1phy1>;
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};
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port@2 {
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reg = <2>;
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label = "lan4";
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phy-mode = "internal";
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phy-handle = <&t1phy2>;
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};
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port@3 {
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reg = <3>;
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label = "lan6";
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phy-mode = "internal";
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phy-handle = <&t1phy3>;
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};
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port@4 {
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reg = <4>;
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phy-mode = "rgmii";
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tx-internal-delay-ps = <2000>;
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rx-internal-delay-ps = <2000>;
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ethernet = <&macb0>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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port@5 {
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reg = <5>;
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label = "lan7";
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phy-mode = "rgmii";
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tx-internal-delay-ps = <2000>;
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rx-internal-delay-ps = <2000>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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port@6 {
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reg = <6>;
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label = "lan5";
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phy-mode = "internal";
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phy-handle = <&t1phy6>;
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};
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port@7 {
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reg = <7>;
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label = "lan3";
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phy-mode = "internal";
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phy-handle = <&t1phy7>;
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};
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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t1phy0: ethernet-phy@0{
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reg = <0x0>;
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};
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t1phy1: ethernet-phy@1{
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reg = <0x1>;
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};
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t1phy2: ethernet-phy@2{
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reg = <0x2>;
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};
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t1phy3: ethernet-phy@3{
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reg = <0x3>;
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};
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t1phy6: ethernet-phy@6{
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reg = <0x6>;
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};
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t1phy7: ethernet-phy@7{
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reg = <0x7>;
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};
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};
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};
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};
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