55af415b42
Meson8b is a cost reduced variant of the Meson8 SoC. It's package size is smaller than Meson8. Unfortunately there are a few key differences which cannot be seen without close inspection of the code and the public S805 datasheet: - the GPIOX bank is missing the GPIOX_12, GPIOX_13, GPIOX_14 and GPIOX_15 GPIOs - the GPIOY bank is missing the GPIOY_2, GPIOY_4, GPIOY_5, GPIOY_15 and GPIOY_16 GPIOs - the GPIODV bank is missing all GPIOs except GPIODV_9, GPIODV_24, GPIODV_25, GPIODV_26, GPIODV_27, GPIODV_28 and GPIODV_29 - the GPIOZ bank is missing completely - there is a new GPIO bank called "DIF" This means that Meson8b only has 83 actual GPIO lines. Without any holes there would be 130 GPIO lines in total (120 are inherited from Meson8 plus 10 new from the DIF bank). GPIOs greater GPIOZ_3 (whose ID is 83 - as a reminder: this is exactly the number of actual GPIO lines on Meson8b and also the value of meson8b_cbus_pinctrl_data.num_pins) cannot berequested. Using CARD_6 (which used ID 100 prior to this patch, "base of the GPIO controller was 382) as an example: $ echo 482 > /sys/class/gpio/export export_store: invalid GPIO 482 This removes all non-existing pins from to dt-bindings header file (include/dt-bindings/gpio/meson8b-gpio.h). This allows us to have a consecutive numbering for the GPIO #defines (GPIOY_2 doesn't exist for example, so previously the GPIOY_3 ID was "GPIOY_1 + 2", after this patch it is "GPIOY_1 + 1"). As a nice side-effect this means that we get compile-time (instead of runtime) errors if Meson8b .dts uses a pin that only exists on Meson8. Additionally the pinctrl-meson8b driver has to be updated to handle this new GPIO numbering. By default a struct meson_bank only handles GPIO banks where the pins are numbered consecutively because it calculates the bit offsets based on the GPIO IDs. This is solved by taking the original BANK() definition and splitting it into consecutive subsets (X0..11 and X16..21). The bit offsets for each new bank includes the skipped GPIOs (the definition of the "X0..11" bank is identical to the old "X" bank apart from the "last IRQ" field, the definition of the new, split "X16..21" bank takes the original "X" bank and adds 16 - the start of the new split bank - to the "first IRQ", pullen bit, pull bit, dir bit, out bit and in bit). Commit984cffdeae("pinctrl: Fix gpio/pin mapping for Meson8b") fixed the same issue by setting "ngpio" (of the gpio_chip) to 130. Unfortunately this broke indb80f0e158("pinctrl: meson: get rid of unneeded domain structures"). The solution from this patch was considered to be better than the previous attempt at fixing this because it provides compile-time error checking for the GPIOs that exist on Meson8 but don't exist on Meson8b. The following pins were tested on an Odroid-C1 using the sysfs GPIO interface checking that their value (high or low) could be read: - GPIOX_0, GPIOX_1, GPIOX_2, GPIOX_3, GPIOX_4, GPIOX_5, GPIOX_6, GPIOX_7, GPIOX_8, GPIOX_9, GPIOX_10, GPIOX_11, GPIOX_18, GPIOX_19, GPIOX_20, GPIOX_21 - GPIOY_3, GPIOY_7, GPIOY_8 (some of these had to be pulled up because they were low by default, others were high by default so these had to be pulled down) Reported-by: Linus Lüssing <linus.luessing@c0d3.blue> Suggested-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
128 lines
2.5 KiB
C
128 lines
2.5 KiB
C
/*
|
|
* GPIO definitions for Amlogic Meson8b SoCs
|
|
*
|
|
* Copyright (C) 2015 Endless Mobile, Inc.
|
|
* Author: Carlo Caione <carlo@endlessm.com>
|
|
*
|
|
* This program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License
|
|
* version 2 as published by the Free Software Foundation.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
|
*/
|
|
|
|
#ifndef _DT_BINDINGS_MESON8B_GPIO_H
|
|
#define _DT_BINDINGS_MESON8B_GPIO_H
|
|
|
|
/* EE (CBUS) GPIO chip */
|
|
#define GPIOX_0 0
|
|
#define GPIOX_1 1
|
|
#define GPIOX_2 2
|
|
#define GPIOX_3 3
|
|
#define GPIOX_4 4
|
|
#define GPIOX_5 5
|
|
#define GPIOX_6 6
|
|
#define GPIOX_7 7
|
|
#define GPIOX_8 8
|
|
#define GPIOX_9 9
|
|
#define GPIOX_10 10
|
|
#define GPIOX_11 11
|
|
#define GPIOX_16 12
|
|
#define GPIOX_17 13
|
|
#define GPIOX_18 14
|
|
#define GPIOX_19 15
|
|
#define GPIOX_20 16
|
|
#define GPIOX_21 17
|
|
|
|
#define GPIOY_0 18
|
|
#define GPIOY_1 19
|
|
#define GPIOY_3 20
|
|
#define GPIOY_6 21
|
|
#define GPIOY_7 22
|
|
#define GPIOY_8 23
|
|
#define GPIOY_9 24
|
|
#define GPIOY_10 25
|
|
#define GPIOY_11 26
|
|
#define GPIOY_12 27
|
|
#define GPIOY_13 28
|
|
#define GPIOY_14 29
|
|
|
|
#define GPIODV_9 30
|
|
#define GPIODV_24 31
|
|
#define GPIODV_25 32
|
|
#define GPIODV_26 33
|
|
#define GPIODV_27 34
|
|
#define GPIODV_28 35
|
|
#define GPIODV_29 36
|
|
|
|
#define GPIOH_0 37
|
|
#define GPIOH_1 38
|
|
#define GPIOH_2 39
|
|
#define GPIOH_3 40
|
|
#define GPIOH_4 41
|
|
#define GPIOH_5 42
|
|
#define GPIOH_6 43
|
|
#define GPIOH_7 44
|
|
#define GPIOH_8 45
|
|
#define GPIOH_9 46
|
|
|
|
#define CARD_0 47
|
|
#define CARD_1 48
|
|
#define CARD_2 49
|
|
#define CARD_3 50
|
|
#define CARD_4 51
|
|
#define CARD_5 52
|
|
#define CARD_6 53
|
|
|
|
#define BOOT_0 54
|
|
#define BOOT_1 55
|
|
#define BOOT_2 56
|
|
#define BOOT_3 57
|
|
#define BOOT_4 58
|
|
#define BOOT_5 59
|
|
#define BOOT_6 60
|
|
#define BOOT_7 61
|
|
#define BOOT_8 62
|
|
#define BOOT_9 63
|
|
#define BOOT_10 64
|
|
#define BOOT_11 65
|
|
#define BOOT_12 66
|
|
#define BOOT_13 67
|
|
#define BOOT_14 68
|
|
#define BOOT_15 69
|
|
#define BOOT_16 70
|
|
#define BOOT_17 71
|
|
#define BOOT_18 72
|
|
|
|
#define DIF_0_P 73
|
|
#define DIF_0_N 74
|
|
#define DIF_1_P 75
|
|
#define DIF_1_N 76
|
|
#define DIF_2_P 77
|
|
#define DIF_2_N 78
|
|
#define DIF_3_P 79
|
|
#define DIF_3_N 80
|
|
#define DIF_4_P 81
|
|
#define DIF_4_N 82
|
|
|
|
/* AO GPIO chip */
|
|
#define GPIOAO_0 0
|
|
#define GPIOAO_1 1
|
|
#define GPIOAO_2 2
|
|
#define GPIOAO_3 3
|
|
#define GPIOAO_4 4
|
|
#define GPIOAO_5 5
|
|
#define GPIOAO_6 6
|
|
#define GPIOAO_7 7
|
|
#define GPIOAO_8 8
|
|
#define GPIOAO_9 9
|
|
#define GPIOAO_10 10
|
|
#define GPIOAO_11 11
|
|
#define GPIOAO_12 12
|
|
#define GPIOAO_13 13
|
|
#define GPIO_BSD_EN 14
|
|
#define GPIO_TEST_N 15
|
|
|
|
#endif /* _DT_BINDINGS_MESON8B_GPIO_H */
|