1d6aa08c54
In oxnas_stdclk_probe(), we need to hold the reference returned by
of_get_parent() and use it to call of_node_put() for refcount
balance.
Fixes: 0bbd72b4c6 ("clk: Add Oxford Semiconductor OXNAS Standard Clocks")
Signed-off-by: Liang He <windhl@126.com>
Link: https://lore.kernel.org/r/20220628143155.170550-1-windhl@126.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
252 lines
6.5 KiB
C
252 lines
6.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2010 Broadcom
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* Copyright (C) 2012 Stephen Warren
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* Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/stringify.h>
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#include <linux/regmap.h>
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#include <linux/mfd/syscon.h>
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#include <dt-bindings/clock/oxsemi,ox810se.h>
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#include <dt-bindings/clock/oxsemi,ox820.h>
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/* Standard regmap gate clocks */
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struct clk_oxnas_gate {
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struct clk_hw hw;
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unsigned int bit;
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struct regmap *regmap;
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};
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struct oxnas_stdclk_data {
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struct clk_hw_onecell_data *onecell_data;
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struct clk_oxnas_gate **gates;
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unsigned int ngates;
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struct clk_oxnas_pll **plls;
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unsigned int nplls;
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};
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/* Regmap offsets */
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#define CLK_STAT_REGOFFSET 0x24
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#define CLK_SET_REGOFFSET 0x2c
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#define CLK_CLR_REGOFFSET 0x30
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static inline struct clk_oxnas_gate *to_clk_oxnas_gate(struct clk_hw *hw)
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{
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return container_of(hw, struct clk_oxnas_gate, hw);
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}
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static int oxnas_clk_gate_is_enabled(struct clk_hw *hw)
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{
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struct clk_oxnas_gate *std = to_clk_oxnas_gate(hw);
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int ret;
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unsigned int val;
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ret = regmap_read(std->regmap, CLK_STAT_REGOFFSET, &val);
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if (ret < 0)
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return ret;
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return val & BIT(std->bit);
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}
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static int oxnas_clk_gate_enable(struct clk_hw *hw)
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{
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struct clk_oxnas_gate *std = to_clk_oxnas_gate(hw);
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regmap_write(std->regmap, CLK_SET_REGOFFSET, BIT(std->bit));
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return 0;
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}
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static void oxnas_clk_gate_disable(struct clk_hw *hw)
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{
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struct clk_oxnas_gate *std = to_clk_oxnas_gate(hw);
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regmap_write(std->regmap, CLK_CLR_REGOFFSET, BIT(std->bit));
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}
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static const struct clk_ops oxnas_clk_gate_ops = {
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.enable = oxnas_clk_gate_enable,
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.disable = oxnas_clk_gate_disable,
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.is_enabled = oxnas_clk_gate_is_enabled,
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};
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static const char *const osc_parents[] = {
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"oscillator",
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};
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static const char *const eth_parents[] = {
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"gmacclk",
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};
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#define OXNAS_GATE(_name, _bit, _parents) \
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struct clk_oxnas_gate _name = { \
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.bit = (_bit), \
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.hw.init = &(struct clk_init_data) { \
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.name = #_name, \
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.ops = &oxnas_clk_gate_ops, \
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.parent_names = _parents, \
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.num_parents = ARRAY_SIZE(_parents), \
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.flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \
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}, \
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}
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static OXNAS_GATE(ox810se_leon, 0, osc_parents);
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static OXNAS_GATE(ox810se_dma_sgdma, 1, osc_parents);
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static OXNAS_GATE(ox810se_cipher, 2, osc_parents);
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static OXNAS_GATE(ox810se_sata, 4, osc_parents);
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static OXNAS_GATE(ox810se_audio, 5, osc_parents);
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static OXNAS_GATE(ox810se_usbmph, 6, osc_parents);
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static OXNAS_GATE(ox810se_etha, 7, eth_parents);
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static OXNAS_GATE(ox810se_pciea, 8, osc_parents);
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static OXNAS_GATE(ox810se_nand, 9, osc_parents);
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static struct clk_oxnas_gate *ox810se_gates[] = {
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&ox810se_leon,
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&ox810se_dma_sgdma,
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&ox810se_cipher,
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&ox810se_sata,
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&ox810se_audio,
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&ox810se_usbmph,
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&ox810se_etha,
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&ox810se_pciea,
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&ox810se_nand,
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};
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static OXNAS_GATE(ox820_leon, 0, osc_parents);
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static OXNAS_GATE(ox820_dma_sgdma, 1, osc_parents);
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static OXNAS_GATE(ox820_cipher, 2, osc_parents);
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static OXNAS_GATE(ox820_sd, 3, osc_parents);
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static OXNAS_GATE(ox820_sata, 4, osc_parents);
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static OXNAS_GATE(ox820_audio, 5, osc_parents);
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static OXNAS_GATE(ox820_usbmph, 6, osc_parents);
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static OXNAS_GATE(ox820_etha, 7, eth_parents);
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static OXNAS_GATE(ox820_pciea, 8, osc_parents);
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static OXNAS_GATE(ox820_nand, 9, osc_parents);
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static OXNAS_GATE(ox820_ethb, 10, eth_parents);
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static OXNAS_GATE(ox820_pcieb, 11, osc_parents);
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static OXNAS_GATE(ox820_ref600, 12, osc_parents);
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static OXNAS_GATE(ox820_usbdev, 13, osc_parents);
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static struct clk_oxnas_gate *ox820_gates[] = {
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&ox820_leon,
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&ox820_dma_sgdma,
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&ox820_cipher,
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&ox820_sd,
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&ox820_sata,
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&ox820_audio,
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&ox820_usbmph,
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&ox820_etha,
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&ox820_pciea,
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&ox820_nand,
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&ox820_etha,
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&ox820_pciea,
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&ox820_ref600,
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&ox820_usbdev,
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};
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static struct clk_hw_onecell_data ox810se_hw_onecell_data = {
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.hws = {
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[CLK_810_LEON] = &ox810se_leon.hw,
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[CLK_810_DMA_SGDMA] = &ox810se_dma_sgdma.hw,
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[CLK_810_CIPHER] = &ox810se_cipher.hw,
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[CLK_810_SATA] = &ox810se_sata.hw,
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[CLK_810_AUDIO] = &ox810se_audio.hw,
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[CLK_810_USBMPH] = &ox810se_usbmph.hw,
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[CLK_810_ETHA] = &ox810se_etha.hw,
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[CLK_810_PCIEA] = &ox810se_pciea.hw,
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[CLK_810_NAND] = &ox810se_nand.hw,
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},
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.num = ARRAY_SIZE(ox810se_gates),
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};
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static struct clk_hw_onecell_data ox820_hw_onecell_data = {
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.hws = {
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[CLK_820_LEON] = &ox820_leon.hw,
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[CLK_820_DMA_SGDMA] = &ox820_dma_sgdma.hw,
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[CLK_820_CIPHER] = &ox820_cipher.hw,
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[CLK_820_SD] = &ox820_sd.hw,
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[CLK_820_SATA] = &ox820_sata.hw,
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[CLK_820_AUDIO] = &ox820_audio.hw,
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[CLK_820_USBMPH] = &ox820_usbmph.hw,
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[CLK_820_ETHA] = &ox820_etha.hw,
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[CLK_820_PCIEA] = &ox820_pciea.hw,
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[CLK_820_NAND] = &ox820_nand.hw,
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[CLK_820_ETHB] = &ox820_ethb.hw,
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[CLK_820_PCIEB] = &ox820_pcieb.hw,
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[CLK_820_REF600] = &ox820_ref600.hw,
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[CLK_820_USBDEV] = &ox820_usbdev.hw,
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},
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.num = ARRAY_SIZE(ox820_gates),
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};
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static struct oxnas_stdclk_data ox810se_stdclk_data = {
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.onecell_data = &ox810se_hw_onecell_data,
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.gates = ox810se_gates,
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.ngates = ARRAY_SIZE(ox810se_gates),
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};
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static struct oxnas_stdclk_data ox820_stdclk_data = {
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.onecell_data = &ox820_hw_onecell_data,
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.gates = ox820_gates,
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.ngates = ARRAY_SIZE(ox820_gates),
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};
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static const struct of_device_id oxnas_stdclk_dt_ids[] = {
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{ .compatible = "oxsemi,ox810se-stdclk", &ox810se_stdclk_data },
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{ .compatible = "oxsemi,ox820-stdclk", &ox820_stdclk_data },
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{ }
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};
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static int oxnas_stdclk_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node, *parent_np;
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const struct oxnas_stdclk_data *data;
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struct regmap *regmap;
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int ret;
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int i;
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data = of_device_get_match_data(&pdev->dev);
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parent_np = of_get_parent(np);
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regmap = syscon_node_to_regmap(parent_np);
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of_node_put(parent_np);
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if (IS_ERR(regmap)) {
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dev_err(&pdev->dev, "failed to have parent regmap\n");
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return PTR_ERR(regmap);
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}
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for (i = 0 ; i < data->ngates ; ++i)
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data->gates[i]->regmap = regmap;
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for (i = 0; i < data->onecell_data->num; i++) {
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if (!data->onecell_data->hws[i])
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continue;
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ret = devm_clk_hw_register(&pdev->dev,
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data->onecell_data->hws[i]);
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if (ret)
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return ret;
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}
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return of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
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data->onecell_data);
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}
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static struct platform_driver oxnas_stdclk_driver = {
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.probe = oxnas_stdclk_probe,
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.driver = {
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.name = "oxnas-stdclk",
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.suppress_bind_attrs = true,
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.of_match_table = oxnas_stdclk_dt_ids,
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},
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};
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builtin_platform_driver(oxnas_stdclk_driver);
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