c94e4ad2d5
Document the UNCACHEABLE_ADDR definitions for footbridge and SA1100 so that we know where they're located and/or what they're accessing. Change RiscPC to calculate the UNCACHEABLE_ADDR value from FLUSH_BASE as that's where we locate that. UNCACHEABLE_ADDR is used to perform an uncached access (ARMv4 terminology) necessary to force a CPU clock-switch to the memory- speed clock, as required for entering WFI. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
64 lines
1.4 KiB
C
64 lines
1.4 KiB
C
/*
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* arch/arm/mach-sa1100/include/mach/hardware.h
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*
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* Copyright (C) 1998 Nicolas Pitre <nico@fluxnic.net>
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*
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* This file contains the hardware definitions for SA1100 architecture
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*
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* 2000/05/23 John Dorsey <john+@cs.cmu.edu>
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* Definitions for SA1111 added.
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*/
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#ifndef __ASM_ARCH_HARDWARE_H
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#define __ASM_ARCH_HARDWARE_H
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#define UNCACHEABLE_ADDR 0xfa050000 /* ICIP */
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/*
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* SA1100 internal I/O mappings
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*
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* We have the following mapping:
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* phys virt
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* 80000000 f8000000
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* 90000000 fa000000
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* a0000000 fc000000
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* b0000000 fe000000
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*/
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#define VIO_BASE 0xf8000000 /* virtual start of IO space */
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#define VIO_SHIFT 3 /* x = IO space shrink power */
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#define PIO_START 0x80000000 /* physical start of IO space */
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#define io_p2v( x ) \
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IOMEM( (((x)&0x00ffffff) | (((x)&0x30000000)>>VIO_SHIFT)) + VIO_BASE )
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#define io_v2p( x ) \
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( (((x)&0x00ffffff) | (((x)&(0x30000000>>VIO_SHIFT))<<VIO_SHIFT)) + PIO_START )
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#define __MREG(x) IOMEM(io_p2v(x))
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#ifndef __ASSEMBLY__
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# define __REG(x) (*((volatile unsigned long __iomem *)io_p2v(x)))
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# define __PREG(x) (io_v2p((unsigned long)&(x)))
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static inline unsigned long get_clock_tick_rate(void)
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{
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return 3686400;
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}
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#else
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# define __REG(x) io_p2v(x)
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# define __PREG(x) io_v2p(x)
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#endif
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#include "SA-1100.h"
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#ifdef CONFIG_SA1101
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#include "SA-1101.h"
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#endif
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#endif /* _ASM_ARCH_HARDWARE_H */
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