ef3846247b
Add device trees for the MBa6x mainboard with TQMa6Q/QP/DL SoMs. As discussed, all new files are added with GPL-2.0-only license, as they are too tightly intertwined with the SoC DTSIs imx6dl.dtsi and imx6q.dtsi, which are GPL-2.0. Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com> Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
45 lines
949 B
Plaintext
45 lines
949 B
Plaintext
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright 2013 Sascha Hauer, Pengutronix
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*
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* Copyright 2013-2021 TQ-Systems GmbH
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* Author: Markus Niebel <Markus.Niebel@tq-group.com>
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*/
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&ecspi5 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi5_mba6x>;
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cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
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};
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ðphy {
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rxdv-skew-ps = <180>;
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txen-skew-ps = <120>;
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rxd3-skew-ps = <180>;
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rxd2-skew-ps = <180>;
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rxd1-skew-ps = <180>;
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rxd0-skew-ps = <180>;
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txd3-skew-ps = <120>;
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txd2-skew-ps = <0>;
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txd1-skew-ps = <180>;
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txd0-skew-ps = <360>;
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txc-skew-ps = <1860>;
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rxc-skew-ps = <1860>;
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};
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&sata {
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status = "okay";
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};
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&iomuxc {
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pinctrl_ecspi5_mba6x: ecspi5grp-mba6x {
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fsl,pins = <
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/* HYS, SPEED = MED, 100k up, DSE = 011, SRE_FAST */
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MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x1b099
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MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0xb099
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MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0xb099
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MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0xb099 /* eCSPI5 SS0 */
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>;
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};
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};
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