Marc Zyngier 99b6a4013f KVM: arm64: Add handling of AArch32 PCMEID{2,3} PMUv3 registers ...

Despite advertising support for AArch32 PMUv3p1, we fail to handle
the PMCEID{2,3} registers, which conveniently alias with the top
bits of PMCEID{0,1}_EL1.

Implement these registers with the usual AA32(HI/LO) aliasing
mechanism.

Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>

2021-02-03 10:59:26 +00:00

..

boot

ARM: device tree updates for 5.11

2020-12-16 16:27:35 -08:00

configs

ARM: device tree updates for 5.11

2020-12-16 16:27:35 -08:00

crypto

crypto: sha - split sha.h into sha1.h and sha2.h

2020-11-20 14:45:33 +11:00

include

EFI updates collected by Ard Biesheuvel:

2020-12-24 12:40:07 -08:00

kernel

A treewide cleanup of interrupt descriptor (ab)use with all sorts of racy

2020-12-24 13:50:23 -08:00

kvm

KVM: arm64: Add handling of AArch32 PCMEID{2,3} PMUv3 registers

2021-02-03 10:59:26 +00:00

lib

arm64: mte: add in-kernel MTE helpers

2020-12-22 12:55:07 -08:00

mm

kasan, arm64: print report from tag fault handler

2020-12-22 12:55:08 -08:00

net

arm64: bpf: Fix branch offset in JIT

2020-09-17 12:05:36 +01:00

xen

arm64: xen: Use modern annotations for assembly functions

2020-01-09 16:09:42 +00:00

Kbuild

…

Kconfig

EFI updates collected by Ard Biesheuvel:

2020-12-24 12:40:07 -08:00

Kconfig.debug

arm64: remove TEXT_OFFSET randomization

2020-06-15 13:10:59 +01:00

Kconfig.platforms

ARM: device tree updates for 5.11

2020-12-16 16:27:35 -08:00

Makefile

kasan, arm64: expand CONFIG_KASAN checks

2020-12-22 12:55:08 -08:00