Atish Patra 9a2451f186 RISC-V: Avoid using per cpu array for ordered booting ... Currently both order booting and spinwait approach uses a per cpu array to update stack & task pointer. This approach will not work for the following cases. 1. If NR_CPUs are configured to be less than highest hart id. 2. A platform has sparse hartid. This issue can be fixed for ordered booting as the booting cpu brings up one cpu at a time using SBI HSM extension which has opaque parameter that is unused until now. Introduce a common secondary boot data structure that can store the stack and task pointer. Secondary harts will use this data while booting up to setup the sp & tp. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>		2022-01-20 09:26:59 -08:00
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asm	RISC-V: Avoid using per cpu array for ordered booting	2022-01-20 09:26:59 -08:00
uapi/asm	ARM:	2021-11-02 11:24:14 -07:00