9a4da8a5b1
Support PCI adapter interrupts using the Single-IRQ-mode. Single-IRQ-mode disables an adapter IRQ automatically after delivering it until the SIC instruction enables it again. This is used to reduce the number of IRQs for streaming workloads. Up to 64 MSI handlers can be registered per PCI function. A hash table is used to map interrupt numbers to MSI descriptors. The interrupt vector is scanned using the flogr instruction. Only MSI/MSI-X interrupts are supported, no legacy INTs. Signed-off-by: Jan Glauber <jang@linux.vnet.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
119 lines
3.2 KiB
C
119 lines
3.2 KiB
C
#ifndef __ASM_S390_PCI_H
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#define __ASM_S390_PCI_H
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/* must be set before including asm-generic/pci.h */
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#define PCI_DMA_BUS_IS_PHYS (0)
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/* must be set before including pci_clp.h */
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#define PCI_BAR_COUNT 6
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#include <asm-generic/pci.h>
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#include <asm-generic/pci-dma-compat.h>
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#include <asm/pci_clp.h>
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#define PCIBIOS_MIN_IO 0x1000
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#define PCIBIOS_MIN_MEM 0x10000000
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#define pcibios_assign_all_busses() (0)
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void __iomem *pci_iomap(struct pci_dev *, int, unsigned long);
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void pci_iounmap(struct pci_dev *, void __iomem *);
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int pci_domain_nr(struct pci_bus *);
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int pci_proc_domain(struct pci_bus *);
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/* MSI arch hooks */
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#define arch_setup_msi_irqs arch_setup_msi_irqs
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#define arch_teardown_msi_irqs arch_teardown_msi_irqs
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#define ZPCI_BUS_NR 0 /* default bus number */
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#define ZPCI_DEVFN 0 /* default device number */
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/* PCI Function Controls */
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#define ZPCI_FC_FN_ENABLED 0x80
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#define ZPCI_FC_ERROR 0x40
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#define ZPCI_FC_BLOCKED 0x20
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#define ZPCI_FC_DMA_ENABLED 0x10
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struct msi_map {
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unsigned long irq;
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struct msi_desc *msi;
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struct hlist_node msi_chain;
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};
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#define ZPCI_NR_MSI_VECS 64
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#define ZPCI_MSI_MASK (ZPCI_NR_MSI_VECS - 1)
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enum zpci_state {
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ZPCI_FN_STATE_RESERVED,
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ZPCI_FN_STATE_STANDBY,
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ZPCI_FN_STATE_CONFIGURED,
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ZPCI_FN_STATE_ONLINE,
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NR_ZPCI_FN_STATES,
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};
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struct zpci_bar_struct {
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u32 val; /* bar start & 3 flag bits */
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u8 size; /* order 2 exponent */
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u16 map_idx; /* index into bar mapping array */
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};
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/* Private data per function */
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struct zpci_dev {
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struct pci_dev *pdev;
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struct pci_bus *bus;
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struct list_head entry; /* list of all zpci_devices, needed for hotplug, etc. */
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enum zpci_state state;
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u32 fid; /* function ID, used by sclp */
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u32 fh; /* function handle, used by insn's */
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u16 pchid; /* physical channel ID */
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u8 pfgid; /* function group ID */
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u16 domain;
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/* IRQ stuff */
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u64 msi_addr; /* MSI address */
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struct zdev_irq_map *irq_map;
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struct msi_map *msi_map[ZPCI_NR_MSI_VECS];
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unsigned int aisb; /* number of the summary bit */
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struct zpci_bar_struct bars[PCI_BAR_COUNT];
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enum pci_bus_speed max_bus_speed;
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};
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static inline bool zdev_enabled(struct zpci_dev *zdev)
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{
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return (zdev->fh & (1UL << 31)) ? true : false;
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}
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/* -----------------------------------------------------------------------------
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Prototypes
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----------------------------------------------------------------------------- */
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/* Base stuff */
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struct zpci_dev *zpci_alloc_device(void);
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int zpci_create_device(struct zpci_dev *);
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int zpci_enable_device(struct zpci_dev *);
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void zpci_stop_device(struct zpci_dev *);
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void zpci_free_device(struct zpci_dev *);
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int zpci_scan_device(struct zpci_dev *);
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/* CLP */
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int clp_find_pci_devices(void);
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int clp_add_pci_device(u32, u32, int);
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int clp_enable_fh(struct zpci_dev *, u8);
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int clp_disable_fh(struct zpci_dev *);
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/* MSI */
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struct msi_desc *__irq_get_msi_desc(unsigned int);
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int zpci_msi_set_mask_bits(struct msi_desc *, u32, u32);
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int zpci_setup_msi_irq(struct zpci_dev *, struct msi_desc *, unsigned int, int);
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void zpci_teardown_msi_irq(struct zpci_dev *, struct msi_desc *);
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int zpci_msihash_init(void);
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void zpci_msihash_exit(void);
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/* Helpers */
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struct zpci_dev *get_zdev(struct pci_dev *);
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struct zpci_dev *get_zdev_by_fid(u32);
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bool zpci_fid_present(u32);
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#endif
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