Clément Péron c02b397e8a ARM: debug: enable UART1 for socfpga Cyclone5
[ Upstream commit f6628486c8489e91c513b62608f89ccdb745600d ]

Cyclone5 and Arria10 doesn't have the same memory map for UART1.

Split the SOCFPGA_UART1 into 2 options to allow debugging on UART1 for Cyclone5.

Signed-off-by: Clément Péron <peron.clem@gmail.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-12-17 20:38:18 +01:00
..
2019-02-20 10:20:53 +01:00
2019-12-01 09:14:21 +01:00
2018-02-28 10:19:44 +01:00
2019-12-05 15:37:49 +01:00