69d41115b8
Add StarFive JH7110 SoC PCIe 2.0 PHY dt-binding. PCIe PHY0 (phy@10210000) can be used as USB 3.0 PHY. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230629075115.11934-3-minda.chen@starfivetech.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
59 lines
1.7 KiB
YAML
59 lines
1.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/starfive,jh7110-pcie-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive JH7110 PCIe 2.0 PHY
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maintainers:
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- Minda Chen <minda.chen@starfivetech.com>
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properties:
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compatible:
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const: starfive,jh7110-pcie-phy
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reg:
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maxItems: 1
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"#phy-cells":
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const: 0
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starfive,sys-syscon:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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- items:
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- description: phandle to System Register Controller sys_syscon node.
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- description: PHY connect offset of SYS_SYSCONSAIF__SYSCFG register for USB PHY.
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description:
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The phandle to System Register Controller syscon node and the PHY connect offset
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of SYS_SYSCONSAIF__SYSCFG register. Connect PHY to USB3 controller.
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starfive,stg-syscon:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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- items:
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- description: phandle to System Register Controller stg_syscon node.
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- description: PHY mode offset of STG_SYSCONSAIF__SYSCFG register.
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- description: PHY enable for USB offset of STG_SYSCONSAIF__SYSCFG register.
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description:
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The phandle to System Register Controller syscon node and the offset
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of STG_SYSCONSAIF__SYSCFG register for PCIe PHY. Total 2 regsisters offset.
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required:
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- compatible
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- reg
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- "#phy-cells"
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additionalProperties: false
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examples:
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- |
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phy@10210000 {
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compatible = "starfive,jh7110-pcie-phy";
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reg = <0x10210000 0x10000>;
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#phy-cells = <0>;
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starfive,sys-syscon = <&sys_syscon 0x18>;
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starfive,stg-syscon = <&stg_syscon 0x148 0x1f4>;
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};
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