9c92ab6191
Based on 1 normalized pattern(s): this software is licensed under the terms of the gnu general public license version 2 as published by the free software foundation and may be copied distributed and modified under those terms this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 285 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141900.642774971@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
63 lines
1.8 KiB
C
63 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* arch/arm/mach-tegra/reset.h
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*
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* CPU reset dispatcher.
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*
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* Copyright (c) 2011, NVIDIA Corporation.
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*/
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#ifndef __MACH_TEGRA_RESET_H
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#define __MACH_TEGRA_RESET_H
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#define TEGRA_RESET_MASK_PRESENT 0
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#define TEGRA_RESET_MASK_LP1 1
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#define TEGRA_RESET_MASK_LP2 2
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#define TEGRA_RESET_STARTUP_SECONDARY 3
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#define TEGRA_RESET_STARTUP_LP2 4
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#define TEGRA_RESET_STARTUP_LP1 5
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#define TEGRA_RESET_RESETTABLE_STATUS 6
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#define TEGRA_RESET_TF_PRESENT 7
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#define TEGRA_RESET_DATA_SIZE 8
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#define RESET_DATA(x) ((TEGRA_RESET_##x)*4)
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#ifndef __ASSEMBLY__
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#include "irammap.h"
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extern unsigned long __tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE];
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void __tegra_cpu_reset_handler_start(void);
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void __tegra_cpu_reset_handler(void);
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void __tegra20_cpu1_resettable_status_offset(void);
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void __tegra_cpu_reset_handler_end(void);
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#ifdef CONFIG_PM_SLEEP
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#define tegra_cpu_lp1_mask \
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(IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
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((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP1] - \
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(u32)__tegra_cpu_reset_handler_start)))
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#define tegra_cpu_lp2_mask \
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(IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
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((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP2] - \
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(u32)__tegra_cpu_reset_handler_start)))
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#define tegra20_cpu1_resettable_status \
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(IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
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((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_RESETTABLE_STATUS] - \
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(u32)__tegra_cpu_reset_handler_start)))
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#endif
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#define tegra_cpu_reset_handler_offset \
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((u32)__tegra_cpu_reset_handler - \
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(u32)__tegra_cpu_reset_handler_start)
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#define tegra_cpu_reset_handler_size \
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(__tegra_cpu_reset_handler_end - \
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__tegra_cpu_reset_handler_start)
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void __init tegra_cpu_reset_handler_init(void);
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#endif
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#endif
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