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Currently the rxe driver has a rxe_mw struct object but nothing about memory windows is enabled. This patch turns on memory windows and some minor cleanup. Set device attribute in rxe.c so max_mw = MAX_MW. Change parameters in rxe_param.h so that MAX_MW is the same as MAX_MR. Reduce the number of MRs and MWs to 4K from 256K. Add device capability bits for 2a and 2b memory windows. Removed RXE_MR_TYPE_MW from the rxe_mr_type enum. Link: https://lore.kernel.org/r/20210608042552.33275-4-rpearsonhpe@gmail.com Signed-off-by: Bob Pearson <rpearsonhpe@gmail.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
142 lines
3.6 KiB
C
142 lines
3.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
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/*
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* Copyright (c) 2016 Mellanox Technologies Ltd. All rights reserved.
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* Copyright (c) 2015 System Fabric Works, Inc. All rights reserved.
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*/
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#ifndef RXE_PARAM_H
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#define RXE_PARAM_H
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#include <uapi/rdma/rdma_user_rxe.h>
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static inline enum ib_mtu rxe_mtu_int_to_enum(int mtu)
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{
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if (mtu < 256)
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return 0;
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else if (mtu < 512)
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return IB_MTU_256;
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else if (mtu < 1024)
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return IB_MTU_512;
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else if (mtu < 2048)
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return IB_MTU_1024;
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else if (mtu < 4096)
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return IB_MTU_2048;
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else
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return IB_MTU_4096;
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}
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/* Find the IB mtu for a given network MTU. */
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static inline enum ib_mtu eth_mtu_int_to_enum(int mtu)
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{
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mtu -= RXE_MAX_HDR_LENGTH;
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return rxe_mtu_int_to_enum(mtu);
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}
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/* default/initial rxe device parameter settings */
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enum rxe_device_param {
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RXE_MAX_MR_SIZE = -1ull,
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RXE_PAGE_SIZE_CAP = 0xfffff000,
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RXE_MAX_QP_WR = 0x4000,
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RXE_DEVICE_CAP_FLAGS = IB_DEVICE_BAD_PKEY_CNTR
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| IB_DEVICE_BAD_QKEY_CNTR
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| IB_DEVICE_AUTO_PATH_MIG
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| IB_DEVICE_CHANGE_PHY_PORT
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| IB_DEVICE_UD_AV_PORT_ENFORCE
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| IB_DEVICE_PORT_ACTIVE_EVENT
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| IB_DEVICE_SYS_IMAGE_GUID
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| IB_DEVICE_RC_RNR_NAK_GEN
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| IB_DEVICE_SRQ_RESIZE
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| IB_DEVICE_MEM_MGT_EXTENSIONS
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| IB_DEVICE_ALLOW_USER_UNREG
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| IB_DEVICE_MEM_WINDOW
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| IB_DEVICE_MEM_WINDOW_TYPE_2A
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| IB_DEVICE_MEM_WINDOW_TYPE_2B,
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RXE_MAX_SGE = 32,
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RXE_MAX_WQE_SIZE = sizeof(struct rxe_send_wqe) +
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sizeof(struct ib_sge) * RXE_MAX_SGE,
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RXE_MAX_INLINE_DATA = RXE_MAX_WQE_SIZE -
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sizeof(struct rxe_send_wqe),
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RXE_MAX_SGE_RD = 32,
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RXE_MAX_CQ = 16384,
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RXE_MAX_LOG_CQE = 15,
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RXE_MAX_PD = 0x7ffc,
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RXE_MAX_QP_RD_ATOM = 128,
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RXE_MAX_RES_RD_ATOM = 0x3f000,
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RXE_MAX_QP_INIT_RD_ATOM = 128,
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RXE_MAX_MCAST_GRP = 8192,
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RXE_MAX_MCAST_QP_ATTACH = 56,
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RXE_MAX_TOT_MCAST_QP_ATTACH = 0x70000,
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RXE_MAX_AH = 100,
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RXE_MAX_SRQ_WR = 0x4000,
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RXE_MIN_SRQ_WR = 1,
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RXE_MAX_SRQ_SGE = 27,
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RXE_MIN_SRQ_SGE = 1,
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RXE_MAX_FMR_PAGE_LIST_LEN = 512,
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RXE_MAX_PKEYS = 1,
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RXE_LOCAL_CA_ACK_DELAY = 15,
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RXE_MAX_UCONTEXT = 512,
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RXE_NUM_PORT = 1,
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RXE_MAX_QP = 0x10000,
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RXE_MIN_QP_INDEX = 16,
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RXE_MAX_QP_INDEX = 0x00020000,
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RXE_MAX_SRQ = 0x00001000,
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RXE_MIN_SRQ_INDEX = 0x00020001,
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RXE_MAX_SRQ_INDEX = 0x00040000,
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RXE_MAX_MR = 0x00001000,
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RXE_MAX_MW = 0x00001000,
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RXE_MIN_MR_INDEX = 0x00000001,
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RXE_MAX_MR_INDEX = 0x00010000,
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RXE_MIN_MW_INDEX = 0x00010001,
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RXE_MAX_MW_INDEX = 0x00020000,
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RXE_MAX_PKT_PER_ACK = 64,
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RXE_MAX_UNACKED_PSNS = 128,
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/* Max inflight SKBs per queue pair */
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RXE_INFLIGHT_SKBS_PER_QP_HIGH = 64,
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RXE_INFLIGHT_SKBS_PER_QP_LOW = 16,
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/* Delay before calling arbiter timer */
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RXE_NSEC_ARB_TIMER_DELAY = 200,
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/* IBTA v1.4 A3.3.1 VENDOR INFORMATION section */
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RXE_VENDOR_ID = 0XFFFFFF,
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};
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/* default/initial rxe port parameters */
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enum rxe_port_param {
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RXE_PORT_GID_TBL_LEN = 1024,
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RXE_PORT_PORT_CAP_FLAGS = RDMA_CORE_CAP_PROT_ROCE_UDP_ENCAP,
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RXE_PORT_MAX_MSG_SZ = 0x800000,
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RXE_PORT_BAD_PKEY_CNTR = 0,
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RXE_PORT_QKEY_VIOL_CNTR = 0,
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RXE_PORT_LID = 0,
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RXE_PORT_SM_LID = 0,
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RXE_PORT_SM_SL = 0,
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RXE_PORT_LMC = 0,
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RXE_PORT_MAX_VL_NUM = 1,
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RXE_PORT_SUBNET_TIMEOUT = 0,
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RXE_PORT_INIT_TYPE_REPLY = 0,
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RXE_PORT_ACTIVE_WIDTH = IB_WIDTH_1X,
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RXE_PORT_ACTIVE_SPEED = 1,
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RXE_PORT_PKEY_TBL_LEN = 1,
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RXE_PORT_PHYS_STATE = IB_PORT_PHYS_STATE_POLLING,
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RXE_PORT_SUBNET_PREFIX = 0xfe80000000000000ULL,
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};
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/* default/initial port info parameters */
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enum rxe_port_info_param {
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RXE_PORT_INFO_VL_CAP = 4, /* 1-8 */
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RXE_PORT_INFO_MTU_CAP = 5, /* 4096 */
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RXE_PORT_INFO_OPER_VL = 1, /* 1 */
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};
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#endif /* RXE_PARAM_H */
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