8918465163
The memory controller on NVIDIA Tegra exposes various knobs that can be used to tune the behaviour of the clients attached to it. Currently this driver sets up the latency allowance registers to the HW defaults. Eventually an API should be exported by this driver (via a custom API or a generic subsystem) to allow clients to register latency requirements. This driver also registers an IOMMU (SMMU) that's implemented by the memory controller. It is supported on Tegra30, Tegra114 and Tegra124 currently. Tegra20 has a GART instead. The Tegra SMMU operates on memory clients and SWGROUPs. A memory client is a unidirectional, special-purpose DMA master. A SWGROUP represents a set of memory clients that form a logical functional unit corresponding to a single device. Typically a device has two clients: one client for read transactions and one client for write transactions, but there are also devices that have only read clients, but many of them (such as the display controllers). Because there is no 1:1 relationship between memory clients and devices the driver keeps a table of memory clients and the SWGROUPs that they belong to per SoC. Note that this is an exception and due to the fact that the SMMU is tightly integrated with the rest of the Tegra SoC. The use of these tables is discouraged in drivers for generic IOMMU devices such as the ARM SMMU because the same IOMMU could be used in any number of SoCs and keeping such tables for each SoC would not scale. Acked-by: Joerg Roedel <jroedel@suse.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
306 lines
8.7 KiB
Plaintext
306 lines
8.7 KiB
Plaintext
# IOMMU_API always gets selected by whoever wants it.
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config IOMMU_API
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bool
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menuconfig IOMMU_SUPPORT
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bool "IOMMU Hardware Support"
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default y
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---help---
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Say Y here if you want to compile device drivers for IO Memory
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Management Units into the kernel. These devices usually allow to
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remap DMA requests and/or remap interrupts from other devices on the
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system.
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if IOMMU_SUPPORT
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config OF_IOMMU
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def_bool y
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depends on OF
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config FSL_PAMU
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bool "Freescale IOMMU support"
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depends on PPC_E500MC
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select IOMMU_API
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select GENERIC_ALLOCATOR
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help
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Freescale PAMU support. PAMU is the IOMMU present on Freescale QorIQ platforms.
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PAMU can authorize memory access, remap the memory address, and remap I/O
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transaction types.
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# MSM IOMMU support
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config MSM_IOMMU
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bool "MSM IOMMU Support"
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depends on ARCH_MSM8X60 || ARCH_MSM8960
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select IOMMU_API
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help
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Support for the IOMMUs found on certain Qualcomm SOCs.
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These IOMMUs allow virtualization of the address space used by most
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cores within the multimedia subsystem.
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If unsure, say N here.
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config IOMMU_PGTABLES_L2
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def_bool y
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depends on MSM_IOMMU && MMU && SMP && CPU_DCACHE_DISABLE=n
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# AMD IOMMU support
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config AMD_IOMMU
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bool "AMD IOMMU support"
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select SWIOTLB
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select PCI_MSI
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select PCI_ATS
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select PCI_PRI
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select PCI_PASID
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select IOMMU_API
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depends on X86_64 && PCI && ACPI
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---help---
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With this option you can enable support for AMD IOMMU hardware in
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your system. An IOMMU is a hardware component which provides
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remapping of DMA memory accesses from devices. With an AMD IOMMU you
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can isolate the DMA memory of different devices and protect the
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system from misbehaving device drivers or hardware.
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You can find out if your system has an AMD IOMMU if you look into
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your BIOS for an option to enable it or if you have an IVRS ACPI
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table.
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config AMD_IOMMU_STATS
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bool "Export AMD IOMMU statistics to debugfs"
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depends on AMD_IOMMU
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select DEBUG_FS
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---help---
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This option enables code in the AMD IOMMU driver to collect various
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statistics about whats happening in the driver and exports that
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information to userspace via debugfs.
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If unsure, say N.
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config AMD_IOMMU_V2
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tristate "AMD IOMMU Version 2 driver"
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depends on AMD_IOMMU
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select MMU_NOTIFIER
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---help---
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This option enables support for the AMD IOMMUv2 features of the IOMMU
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hardware. Select this option if you want to use devices that support
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the PCI PRI and PASID interface.
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# Intel IOMMU support
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config DMAR_TABLE
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bool
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config INTEL_IOMMU
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bool "Support for Intel IOMMU using DMA Remapping Devices"
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depends on PCI_MSI && ACPI && (X86 || IA64_GENERIC)
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select IOMMU_API
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select DMAR_TABLE
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help
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DMA remapping (DMAR) devices support enables independent address
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translations for Direct Memory Access (DMA) from devices.
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These DMA remapping devices are reported via ACPI tables
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and include PCI device scope covered by these DMA
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remapping devices.
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config INTEL_IOMMU_DEFAULT_ON
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def_bool y
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prompt "Enable Intel DMA Remapping Devices by default"
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depends on INTEL_IOMMU
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help
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Selecting this option will enable a DMAR device at boot time if
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one is found. If this option is not selected, DMAR support can
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be enabled by passing intel_iommu=on to the kernel.
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config INTEL_IOMMU_BROKEN_GFX_WA
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bool "Workaround broken graphics drivers (going away soon)"
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depends on INTEL_IOMMU && BROKEN && X86
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---help---
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Current Graphics drivers tend to use physical address
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for DMA and avoid using DMA APIs. Setting this config
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option permits the IOMMU driver to set a unity map for
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all the OS-visible memory. Hence the driver can continue
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to use physical addresses for DMA, at least until this
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option is removed in the 2.6.32 kernel.
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config INTEL_IOMMU_FLOPPY_WA
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def_bool y
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depends on INTEL_IOMMU && X86
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---help---
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Floppy disk drivers are known to bypass DMA API calls
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thereby failing to work when IOMMU is enabled. This
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workaround will setup a 1:1 mapping for the first
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16MiB to make floppy (an ISA device) work.
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config IRQ_REMAP
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bool "Support for Interrupt Remapping"
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depends on X86_64 && X86_IO_APIC && PCI_MSI && ACPI
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select DMAR_TABLE
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---help---
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Supports Interrupt remapping for IO-APIC and MSI devices.
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To use x2apic mode in the CPU's which support x2APIC enhancements or
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to support platforms with CPU's having > 8 bit APIC ID, say Y.
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# OMAP IOMMU support
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config OMAP_IOMMU
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bool "OMAP IOMMU Support"
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depends on ARCH_OMAP2PLUS
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select IOMMU_API
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config OMAP_IOMMU_DEBUG
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tristate "Export OMAP IOMMU internals in DebugFS"
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depends on OMAP_IOMMU && DEBUG_FS
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help
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Select this to see extensive information about
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the internal state of OMAP IOMMU in debugfs.
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Say N unless you know you need this.
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config TEGRA_IOMMU_GART
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bool "Tegra GART IOMMU Support"
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depends on ARCH_TEGRA_2x_SOC
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select IOMMU_API
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help
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Enables support for remapping discontiguous physical memory
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shared with the operating system into contiguous I/O virtual
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space through the GART (Graphics Address Relocation Table)
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hardware included on Tegra SoCs.
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config TEGRA_IOMMU_SMMU
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bool "NVIDIA Tegra SMMU Support"
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depends on ARCH_TEGRA
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depends on TEGRA_AHB
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depends on TEGRA_MC
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select IOMMU_API
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help
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This driver supports the IOMMU hardware (SMMU) found on NVIDIA Tegra
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SoCs (Tegra30 up to Tegra124).
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config EXYNOS_IOMMU
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bool "Exynos IOMMU Support"
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depends on ARCH_EXYNOS
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select IOMMU_API
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select ARM_DMA_USE_IOMMU
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help
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Support for the IOMMU (System MMU) of Samsung Exynos application
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processor family. This enables H/W multimedia accelerators to see
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non-linear physical memory chunks as linear memory in their
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address space.
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If unsure, say N here.
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config EXYNOS_IOMMU_DEBUG
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bool "Debugging log for Exynos IOMMU"
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depends on EXYNOS_IOMMU
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help
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Select this to see the detailed log message that shows what
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happens in the IOMMU driver.
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Say N unless you need kernel log message for IOMMU debugging.
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config SHMOBILE_IPMMU
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bool
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config SHMOBILE_IPMMU_TLB
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bool
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config SHMOBILE_IOMMU
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bool "IOMMU for Renesas IPMMU/IPMMUI"
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default n
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depends on ARM
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depends on ARCH_SHMOBILE || COMPILE_TEST
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select IOMMU_API
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select ARM_DMA_USE_IOMMU
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select SHMOBILE_IPMMU
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select SHMOBILE_IPMMU_TLB
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help
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Support for Renesas IPMMU/IPMMUI. This option enables
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remapping of DMA memory accesses from all of the IP blocks
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on the ICB.
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Warning: Drivers (including userspace drivers of UIO
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devices) of the IP blocks on the ICB *must* use addresses
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allocated from the IPMMU (iova) for DMA with this option
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enabled.
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If unsure, say N.
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choice
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prompt "IPMMU/IPMMUI address space size"
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default SHMOBILE_IOMMU_ADDRSIZE_2048MB
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depends on SHMOBILE_IOMMU
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help
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This option sets IPMMU/IPMMUI address space size by
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adjusting the 1st level page table size. The page table size
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is calculated as follows:
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page table size = number of page table entries * 4 bytes
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number of page table entries = address space size / 1 MiB
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For example, when the address space size is 2048 MiB, the
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1st level page table size is 8192 bytes.
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config SHMOBILE_IOMMU_ADDRSIZE_2048MB
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bool "2 GiB"
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config SHMOBILE_IOMMU_ADDRSIZE_1024MB
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bool "1 GiB"
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config SHMOBILE_IOMMU_ADDRSIZE_512MB
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bool "512 MiB"
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config SHMOBILE_IOMMU_ADDRSIZE_256MB
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bool "256 MiB"
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config SHMOBILE_IOMMU_ADDRSIZE_128MB
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bool "128 MiB"
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config SHMOBILE_IOMMU_ADDRSIZE_64MB
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bool "64 MiB"
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config SHMOBILE_IOMMU_ADDRSIZE_32MB
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bool "32 MiB"
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endchoice
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config SHMOBILE_IOMMU_L1SIZE
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int
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default 8192 if SHMOBILE_IOMMU_ADDRSIZE_2048MB
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default 4096 if SHMOBILE_IOMMU_ADDRSIZE_1024MB
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default 2048 if SHMOBILE_IOMMU_ADDRSIZE_512MB
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default 1024 if SHMOBILE_IOMMU_ADDRSIZE_256MB
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default 512 if SHMOBILE_IOMMU_ADDRSIZE_128MB
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default 256 if SHMOBILE_IOMMU_ADDRSIZE_64MB
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default 128 if SHMOBILE_IOMMU_ADDRSIZE_32MB
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config IPMMU_VMSA
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bool "Renesas VMSA-compatible IPMMU"
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depends on ARM_LPAE
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depends on ARCH_SHMOBILE || COMPILE_TEST
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select IOMMU_API
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select ARM_DMA_USE_IOMMU
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help
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Support for the Renesas VMSA-compatible IPMMU Renesas found in the
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R-Mobile APE6 and R-Car H2/M2 SoCs.
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If unsure, say N.
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config SPAPR_TCE_IOMMU
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bool "sPAPR TCE IOMMU Support"
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depends on PPC_POWERNV || PPC_PSERIES
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select IOMMU_API
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help
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Enables bits of IOMMU API required by VFIO. The iommu_ops
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is not implemented as it is not necessary for VFIO.
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config ARM_SMMU
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bool "ARM Ltd. System MMU (SMMU) Support"
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depends on ARM64 || (ARM_LPAE && OF)
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select IOMMU_API
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select ARM_DMA_USE_IOMMU if ARM
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help
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Support for implementations of the ARM System MMU architecture
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versions 1 and 2. The driver supports both v7l and v8l table
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formats with 4k and 64k page sizes.
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Say Y here if your SoC includes an IOMMU device implementing
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the ARM SMMU architecture.
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endif # IOMMU_SUPPORT
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