65c9ad77cb
Add a MODULE_DEVICE_TABLE() on all clocks that can be built as modules to allow auto-load at boot. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Miles Chen <miles.chen@mediatek.com> Tested-by: Chen-Yu Tsai <wenst@chromium.org> # MT8183, MT8192, MT8195 Chromebooks Link: https://lore.kernel.org/r/20230306140543.1813621-50-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
104 lines
3.8 KiB
C
104 lines
3.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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//
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// Copyright (c) 2021 MediaTek Inc.
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// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include <dt-bindings/clock/mt8192-clk.h>
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static const struct mtk_gate_regs mm0_cg_regs = {
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.set_ofs = 0x104,
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.clr_ofs = 0x108,
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.sta_ofs = 0x100,
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};
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static const struct mtk_gate_regs mm1_cg_regs = {
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.set_ofs = 0x114,
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.clr_ofs = 0x118,
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.sta_ofs = 0x110,
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};
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static const struct mtk_gate_regs mm2_cg_regs = {
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.set_ofs = 0x1a4,
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.clr_ofs = 0x1a8,
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.sta_ofs = 0x1a0,
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};
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#define GATE_MM0(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
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#define GATE_MM1(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
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#define GATE_MM2(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &mm2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
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static const struct mtk_gate mm_clks[] = {
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/* MM0 */
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GATE_MM0(CLK_MM_DISP_MUTEX0, "mm_disp_mutex0", "disp_sel", 0),
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GATE_MM0(CLK_MM_DISP_CONFIG, "mm_disp_config", "disp_sel", 1),
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GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "disp_sel", 2),
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GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "disp_sel", 3),
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GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "disp_sel", 4),
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GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "disp_sel", 5),
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GATE_MM0(CLK_MM_DISP_UFBC_WDMA0, "mm_disp_ufbc_wdma0", "disp_sel", 6),
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GATE_MM0(CLK_MM_DISP_RSZ0, "mm_disp_rsz0", "disp_sel", 7),
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GATE_MM0(CLK_MM_DISP_AAL0, "mm_disp_aal0", "disp_sel", 8),
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GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "disp_sel", 9),
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GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "disp_sel", 10),
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GATE_MM0(CLK_MM_SMI_INFRA, "mm_smi_infra", "disp_sel", 11),
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GATE_MM0(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "disp_sel", 12),
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GATE_MM0(CLK_MM_DISP_POSTMASK0, "mm_disp_postmask0", "disp_sel", 13),
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GATE_MM0(CLK_MM_DISP_DSC_WRAP0, "mm_disp_dsc_wrap0", "disp_sel", 14),
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GATE_MM0(CLK_MM_DSI0, "mm_dsi0", "disp_sel", 15),
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GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "disp_sel", 16),
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GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "disp_sel", 17),
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GATE_MM0(CLK_MM_DISP_FAKE_ENG0, "mm_disp_fake_eng0", "disp_sel", 18),
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GATE_MM0(CLK_MM_DISP_FAKE_ENG1, "mm_disp_fake_eng1", "disp_sel", 19),
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GATE_MM0(CLK_MM_MDP_TDSHP4, "mm_mdp_tdshp4", "disp_sel", 20),
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GATE_MM0(CLK_MM_MDP_RSZ4, "mm_mdp_rsz4", "disp_sel", 21),
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GATE_MM0(CLK_MM_MDP_AAL4, "mm_mdp_aal4", "disp_sel", 22),
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GATE_MM0(CLK_MM_MDP_HDR4, "mm_mdp_hdr4", "disp_sel", 23),
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GATE_MM0(CLK_MM_MDP_RDMA4, "mm_mdp_rdma4", "disp_sel", 24),
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GATE_MM0(CLK_MM_MDP_COLOR4, "mm_mdp_color4", "disp_sel", 25),
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GATE_MM0(CLK_MM_DISP_Y2R0, "mm_disp_y2r0", "disp_sel", 26),
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GATE_MM0(CLK_MM_SMI_GALS, "mm_smi_gals", "disp_sel", 27),
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GATE_MM0(CLK_MM_DISP_OVL2_2L, "mm_disp_ovl2_2l", "disp_sel", 28),
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GATE_MM0(CLK_MM_DISP_RDMA4, "mm_disp_rdma4", "disp_sel", 29),
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GATE_MM0(CLK_MM_DISP_DPI0, "mm_disp_dpi0", "disp_sel", 30),
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/* MM1 */
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GATE_MM1(CLK_MM_SMI_IOMMU, "mm_smi_iommu", "disp_sel", 0),
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/* MM2 */
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GATE_MM2(CLK_MM_DSI_DSI0, "mm_dsi_dsi0", "disp_sel", 0),
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GATE_MM2(CLK_MM_DPI_DPI0, "mm_dpi_dpi0", "dpi_sel", 8),
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GATE_MM2(CLK_MM_26MHZ, "mm_26mhz", "clk26m", 24),
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GATE_MM2(CLK_MM_32KHZ, "mm_32khz", "clk32k", 25),
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};
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static const struct mtk_clk_desc mm_desc = {
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.clks = mm_clks,
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.num_clks = ARRAY_SIZE(mm_clks),
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};
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static const struct platform_device_id clk_mt8192_mm_id_table[] = {
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{ .name = "clk-mt8192-mm", .driver_data = (kernel_ulong_t)&mm_desc },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(platform, clk_mt8192_mm_id_table);
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static struct platform_driver clk_mt8192_mm_drv = {
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.probe = mtk_clk_pdev_probe,
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.remove = mtk_clk_pdev_remove,
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.driver = {
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.name = "clk-mt8192-mm",
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},
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.id_table = clk_mt8192_mm_id_table,
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};
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module_platform_driver(clk_mt8192_mm_drv);
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MODULE_LICENSE("GPL");
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