Alexandre Ghiti 9e953cda5c riscv: Introduce huge page support for 32/64bit kernel ... This patch implements both 4MB huge page support for 32bit kernel and 2MB/1GB huge pages support for 64bit kernel. Signed-off-by: Alexandre Ghiti <alex@ghiti.fr> Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>		2019-07-03 15:23:38 -07:00
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cacheflush.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286	2019-06-05 17:36:37 +02:00
context.c	riscv: move switch_mm to its own file	2019-05-16 20:42:12 -07:00
extable.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 120	2019-05-24 17:39:02 +02:00
fault.c	riscv: mm: Fix code comment	2019-06-26 15:10:30 -07:00
hugetlbpage.c	riscv: Introduce huge page support for 32/64bit kernel	2019-07-03 15:23:38 -07:00
init.c	RISC-V: Fix memory reservation in setup_bootmem()	2019-07-01 13:24:53 -07:00
ioremap.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286	2019-06-05 17:36:37 +02:00
Makefile	riscv: Introduce huge page support for 32/64bit kernel	2019-07-03 15:23:38 -07:00
sifive_l2_cache.c	RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs	2019-05-16 20:42:13 -07:00