Christophe Leroy 90cbac0e99 powerpc: Enable KFENCE for PPC32 ...

Add architecture specific implementation details for KFENCE and enable
KFENCE for the ppc32 architecture. In particular, this implements the
required interface in <asm/kfence.h>.

KFENCE requires that attributes for pages from its memory pool can
individually be set. Therefore, force the Read/Write linear map to be
mapped at page granularity.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Acked-by: Marco Elver <elver@google.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/8dfe1bd2abde26337c1d8c1ad0acfcc82185e0d5.1614868445.git.christophe.leroy@csgroup.eu

2021-03-24 14:09:30 +11:00

..

8xx.c

powerpc: Enable KFENCE for PPC32

2021-03-24 14:09:30 +11:00

40x.c

mm: remove unneeded includes of <asm/pgalloc.h>

2020-08-07 11:33:26 -07:00

44x.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152

2019-05-30 11:26:32 -07:00

book3e_hugetlbpage.c

powerpc/mm: move FSL_BOOK3 version of update_mmu_cache()

2019-08-20 21:22:14 +10:00

book3e_pgtable.c

powerpc: add support for folded p4d page tables

2020-06-04 19:06:21 -07:00

fsl_booke.c

powerpc: Retire e200 core (mpc555x processor)

2020-12-05 21:49:18 +11:00

kaslr_booke.c

mm: remove unneeded includes of <asm/pgalloc.h>

2020-08-07 11:33:26 -07:00

Makefile

powerpc/fsl_booke/32: implement KASLR infrastructure

2019-11-13 19:27:40 +11:00

mmu_context.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152

2019-05-30 11:26:32 -07:00

tlb_low_64e.S

powerpc/64e: Drop dead BOOK3E_MMU_TLB_STATS code

2020-07-29 21:08:12 +10:00

tlb_low.S

powerpc/44x: Don't support 47x code and non 47x code at the same time

2020-12-04 01:01:34 +11:00

tlb.c

powerpc/8xx: Support 16k hugepages with 4k pages

2020-09-15 22:13:31 +10:00