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Separate out the set_audclk_freq() function into separate functions for the
four families of cores. These cores all use slightly different sample clock
schemes and may be assuming slightly (+/- 3 Hz) different reference frequencies.
The code resuse was not worth the maintenance and testing headache of have all
chips use the same function peppered with conditional logic.
Added comments on how PLL and SRC parameters values are computed. Fixed a few
bugs related to the shared code having a large number of conditional statements.
Noted inconsistencies with FIXME in the comments.
This is done in preparation for getting the CX2388[578] PLL/clock setting logic
cleaned up for CX23888 analog video and IR (which need the VID PLL set right).
Signed-off-by: Andy Walls <awalls@radix.net>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
9eef550a9a