linux/drivers/clk/socfpga
Krzysztof Kozlowski a01be32fcc clk: socfpga: build together Stratix 10, Agilex and N5X clock drivers
On a multiplatform kernel there is little benefit in splitting each
clock driver per platform because space savings are minimal.  Such split
also complicates the code, especially after adding compile testing.

Build all arm64 Intel SoCFPGA clocks together with one entry in
Makefile.  This also removed duplicated line in the Makefile (selecting
common part of clocks per platform).

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2021-03-23 11:03:35 -05:00
..
clk-agilex.c clk: socfpga: agilex: add clock driver for eASIC N5X platform 2021-02-12 13:04:58 -08:00
clk-gate-a10.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201 2019-05-30 11:29:52 -07:00
clk-gate-s10.c clk: socfpga: stratix10: use new parent data scheme 2020-05-26 19:13:05 -07:00
clk-gate.c clk: socfpga: deindent code to proper indentation 2019-08-16 10:20:07 -07:00
clk-periph-a10.c clk: socfpga: Don't reference clk_init_data after registration 2019-08-16 10:20:07 -07:00
clk-periph-s10.c clk: socfpga: agilex: add clock driver for eASIC N5X platform 2021-02-12 13:04:58 -08:00
clk-periph.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157 2019-05-30 11:26:37 -07:00
clk-pll-a10.c clk: socfpga: clk-pll-a10: Remove set but unused variable 'rc' 2021-02-11 11:56:06 -08:00
clk-pll-s10.c clk: socfpga: agilex: add clock driver for eASIC N5X platform 2021-02-12 13:04:58 -08:00
clk-pll.c clk: socfpga: clk-pll: Remove unused variable 'rc' 2021-02-11 11:56:06 -08:00
clk-s10.c clk: socfpga: stratix10: fix the divider for the emac_ptp_free_clk 2020-09-22 12:54:41 -07:00
clk.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 13 2019-05-21 11:28:45 +02:00
clk.h treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288 2019-06-05 17:36:37 +02:00
Kconfig clk: socfpga: build together Stratix 10, Agilex and N5X clock drivers 2021-03-23 11:03:35 -05:00
Makefile clk: socfpga: build together Stratix 10, Agilex and N5X clock drivers 2021-03-23 11:03:35 -05:00
stratix10-clk.h clk: socfpga: agilex: add clock driver for eASIC N5X platform 2021-02-12 13:04:58 -08:00