a06ed27f3b
Though GIC ARE option is disabled for no GIC-v2 compatibility,
Cortex-A72 is free to implement the CPU interface as long as it
communicates with the GIC using the stream protocol. This requires
that the SoC integration mark out the PERIPHBASE[1] as reserved area
within the SoC. See longer discussion in [2] for further information.
Update the GIC register map to indicate offsets from PERIPHBASE based
on [3]. Without doing this, systems like kvm will not function with
gic-v2 emulation.
[1] https://developer.arm.com/documentation/100095/0002/system-control/aarch64-register-descriptions/configuration-base-address-register--el1
[2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/
[3] https://developer.arm.com/documentation/100095/0002/way1382452674438
Cc: stable@vger.kernel.org # 5.10+
Fixes:
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.. | ||
boot | ||
configs | ||
crypto | ||
hyperv | ||
include | ||
kernel | ||
kvm | ||
lib | ||
mm | ||
net | ||
tools | ||
xen | ||
Kbuild | ||
Kconfig | ||
Kconfig.debug | ||
Kconfig.platforms | ||
Makefile |