ec66a97d15
The T1024 SoC includes the following function and features: - Two 64-bit Power architecture e5500 cores, up to 1.4GHz - private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC) - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration - Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI) - High-speed peripheral interfaces - Three PCI Express 2.0 controllers - Additional peripheral interfaces - One SATA 2.0 controller - Two USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/eSDHC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Two 8-channel DMA engines - Multicore programmable interrupt controller (PIC) - LCD interface (DIU) with 12 bit dual data rate - QUICC Engine block supporting TDM, HDLC, and UART - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [scottwood@freescale.com: whitespace fixes] Signed-off-by: Scott Wood <scottwood@freescale.com>
101 lines
3.0 KiB
Plaintext
101 lines
3.0 KiB
Plaintext
/*
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* T1024 Silicon/SoC Device Tree Source (post include)
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*
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* Copyright 2014 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/include/ "t1023si-post.dtsi"
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/ {
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aliases {
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vga = &display;
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display = &display;
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};
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qe:qe@ffe140000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "qe";
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compatible = "fsl,qe";
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ranges = <0x0 0xf 0xfe140000 0x40000>;
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reg = <0xf 0xfe140000 0 0x480>;
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fsl,qe-num-riscs = <1>;
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fsl,qe-num-snums = <28>;
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brg-frequency = <0>;
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bus-frequency = <0>;
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};
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};
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&soc {
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display:display@180000 {
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compatible = "fsl,t1024-diu", "fsl,diu";
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reg = <0x180000 1000>;
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interrupts = <74 2 0 0>;
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};
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};
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&qe {
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qeic: interrupt-controller@80 {
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interrupt-controller;
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compatible = "fsl,qe-ic";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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reg = <0x80 0x80>;
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interrupts = <95 2 0 0 94 2 0 0>; //high:79 low:78
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};
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ucc@2000 {
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cell-index = <1>;
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reg = <0x2000 0x200>;
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interrupts = <32>;
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interrupt-parent = <&qeic>;
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};
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ucc@2200 {
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cell-index = <3>;
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reg = <0x2200 0x200>;
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interrupts = <34>;
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interrupt-parent = <&qeic>;
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};
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muram@10000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,qe-muram", "fsl,cpm-muram";
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ranges = <0x0 0x10000 0x6000>;
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data-only@0 {
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compatible = "fsl,qe-muram-data", "fsl,cpm-muram-data";
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reg = <0x0 0x6000>;
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};
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};
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};
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