a19bffb10c
When host system is under heavy load and the NPU is already running on the lowest frequency, PUNIT may request Duty Cycle Throttling (DCT). This will further reduce NPU power usage. PUNIT requests DCT mode using Survabilty IRQ and mailbox register. The driver then issues a JSM message to the FW that enables the DCT mode. If the NPU resets while in DCT mode, the driver request DCT mode during FW boot. Also add debugfs "dct" file that allows to set arbitrary DCT percentage, which is used by driver tests. Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com> Reviewed-by: Wachowski, Karol <karol.wachowski@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240611120433.1012423-7-jacek.lawrynowicz@linux.intel.com
109 lines
4.6 KiB
C
109 lines
4.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2020-2024 Intel Corporation
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*/
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#ifndef __IVPU_HW_BTRS_LNL_REG_H__
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#define __IVPU_HW_BTRS_LNL_REG_H__
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#include <linux/bits.h>
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#define VPU_HW_BTRS_LNL_INTERRUPT_STAT 0x00000000u
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#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_FREQ_CHANGE_MASK BIT_MASK(0)
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#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_ATS_ERR_MASK BIT_MASK(1)
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#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_CFI0_ERR_MASK BIT_MASK(2)
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#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_CFI1_ERR_MASK BIT_MASK(3)
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#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_IMR0_ERR_MASK BIT_MASK(4)
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#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_IMR1_ERR_MASK BIT_MASK(5)
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#define VPU_HW_BTRS_LNL_INTERRUPT_STAT_SURV_ERR_MASK BIT_MASK(6)
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#define VPU_HW_BTRS_LNL_LOCAL_INT_MASK 0x00000004u
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#define VPU_HW_BTRS_LNL_GLOBAL_INT_MASK 0x00000008u
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#define VPU_HW_BTRS_LNL_HM_ATS 0x0000000cu
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#define VPU_HW_BTRS_LNL_ATS_ERR_LOG1 0x00000010u
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#define VPU_HW_BTRS_LNL_ATS_ERR_LOG2 0x00000014u
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#define VPU_HW_BTRS_LNL_ATS_ERR_CLEAR 0x00000018u
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#define VPU_HW_BTRS_LNL_CFI0_ERR_LOG 0x0000001cu
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#define VPU_HW_BTRS_LNL_CFI0_ERR_CLEAR 0x00000020u
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#define VPU_HW_BTRS_LNL_PORT_ARBITRATION_WEIGHTS_ATS 0x00000024u
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#define VPU_HW_BTRS_LNL_CFI1_ERR_LOG 0x00000040u
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#define VPU_HW_BTRS_LNL_CFI1_ERR_CLEAR 0x00000044u
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#define VPU_HW_BTRS_LNL_IMR_ERR_CFI0_LOW 0x00000048u
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#define VPU_HW_BTRS_LNL_IMR_ERR_CFI0_HIGH 0x0000004cu
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#define VPU_HW_BTRS_LNL_IMR_ERR_CFI0_CLEAR 0x00000050u
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#define VPU_HW_BTRS_LNL_PORT_ARBITRATION_WEIGHTS 0x00000054u
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#define VPU_HW_BTRS_LNL_IMR_ERR_CFI1_LOW 0x00000058u
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#define VPU_HW_BTRS_LNL_IMR_ERR_CFI1_HIGH 0x0000005cu
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#define VPU_HW_BTRS_LNL_IMR_ERR_CFI1_CLEAR 0x00000060u
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#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS 0x00000070u
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#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS_CMD_MASK GENMASK(7, 0)
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#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS_PARAM1_MASK GENMASK(15, 8)
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#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS_PARAM2_MASK GENMASK(23, 16)
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#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS_PARAM3_MASK GENMASK(31, 24)
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#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW 0x00000074u
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#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW_CMD_MASK GENMASK(7, 0)
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#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW_PARAM1_MASK GENMASK(15, 8)
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#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW_PARAM2_MASK GENMASK(23, 16)
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#define VPU_HW_BTRS_LNL_PCODE_MAILBOX_SHADOW_PARAM3_MASK GENMASK(31, 24)
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#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0 0x00000130u
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#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0_MIN_RATIO_MASK GENMASK(15, 0)
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#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0_MAX_RATIO_MASK GENMASK(31, 16)
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#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1 0x00000134u
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#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1_TARGET_RATIO_MASK GENMASK(15, 0)
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#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1_EPP_MASK GENMASK(31, 16)
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#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2 0x00000138u
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#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2_CONFIG_MASK GENMASK(15, 0)
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#define VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2_CDYN_MASK GENMASK(31, 16)
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#define VPU_HW_BTRS_LNL_WP_REQ_CMD 0x0000013cu
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#define VPU_HW_BTRS_LNL_WP_REQ_CMD_SEND_MASK BIT_MASK(0)
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#define VPU_HW_BTRS_LNL_PLL_FREQ 0x00000148u
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#define VPU_HW_BTRS_LNL_PLL_FREQ_RATIO_MASK GENMASK(15, 0)
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#define VPU_HW_BTRS_LNL_TILE_FUSE 0x00000150u
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#define VPU_HW_BTRS_LNL_TILE_FUSE_VALID_MASK BIT_MASK(0)
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#define VPU_HW_BTRS_LNL_TILE_FUSE_CONFIG_MASK GENMASK(6, 1)
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#define VPU_HW_BTRS_LNL_VPU_STATUS 0x00000154u
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#define VPU_HW_BTRS_LNL_VPU_STATUS_READY_MASK BIT_MASK(0)
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#define VPU_HW_BTRS_LNL_VPU_STATUS_IDLE_MASK BIT_MASK(1)
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#define VPU_HW_BTRS_LNL_VPU_STATUS_DUP_IDLE_MASK BIT_MASK(2)
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#define VPU_HW_BTRS_LNL_VPU_STATUS_CLOCK_RESOURCE_OWN_ACK_MASK BIT_MASK(6)
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#define VPU_HW_BTRS_LNL_VPU_STATUS_POWER_RESOURCE_OWN_ACK_MASK BIT_MASK(7)
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#define VPU_HW_BTRS_LNL_VPU_STATUS_PERF_CLK_MASK BIT_MASK(11)
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#define VPU_HW_BTRS_LNL_VPU_STATUS_DISABLE_CLK_RELINQUISH_MASK BIT_MASK(12)
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#define VPU_HW_BTRS_LNL_IP_RESET 0x00000160u
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#define VPU_HW_BTRS_LNL_IP_RESET_TRIGGER_MASK BIT_MASK(0)
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#define VPU_HW_BTRS_LNL_D0I3_CONTROL 0x00000164u
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#define VPU_HW_BTRS_LNL_D0I3_CONTROL_INPROGRESS_MASK BIT_MASK(0)
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#define VPU_HW_BTRS_LNL_D0I3_CONTROL_I3_MASK BIT_MASK(2)
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#define VPU_HW_BTRS_LNL_VPU_TELEMETRY_OFFSET 0x00000168u
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#define VPU_HW_BTRS_LNL_VPU_TELEMETRY_SIZE 0x0000016cu
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#define VPU_HW_BTRS_LNL_VPU_TELEMETRY_ENABLE 0x00000170u
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#define VPU_HW_BTRS_LNL_FMIN_FUSE 0x00000174u
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#define VPU_HW_BTRS_LNL_FMIN_FUSE_MIN_RATIO_MASK GENMASK(7, 0)
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#define VPU_HW_BTRS_LNL_FMIN_FUSE_PN_RATIO_MASK GENMASK(15, 8)
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#define VPU_HW_BTRS_LNL_FMAX_FUSE 0x00000178u
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#define VPU_HW_BTRS_LNL_FMAX_FUSE_MAX_RATIO_MASK GENMASK(7, 0)
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#endif /* __IVPU_HW_BTRS_LNL_REG_H__ */
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