José Roberto de Souza a1c5f1510b drm/i915/tgl: Update DPLL clock reference register
This register definition changed from ICL and has now another meaning.
Use the right bits on TGL.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190711173115.28296-22-lucas.demarchi@intel.com
2019-07-11 16:31:27 -07:00
..
2019-07-04 14:09:50 +10:00
2019-06-19 12:07:29 +02:00
2019-06-19 12:07:29 +02:00
2019-06-19 12:07:29 +02:00
2019-06-19 12:07:29 +02:00
2019-06-19 12:07:29 +02:00
2019-06-27 11:48:10 +10:00
2019-06-19 12:07:29 +02:00
2019-06-19 12:07:29 +02:00
2019-06-19 12:07:29 +02:00
2019-06-19 12:07:29 +02:00
2019-06-19 12:07:29 +02:00
2019-06-19 12:07:29 +02:00
2019-06-19 12:07:29 +02:00
2019-06-19 12:07:29 +02:00
2019-06-05 20:31:19 +02:00
2019-06-05 20:31:04 +02:00
2019-06-05 20:29:57 +02:00
2019-06-20 17:03:24 +02:00
2019-06-19 12:07:29 +02:00
2019-06-25 12:59:43 +10:00
2019-05-28 08:59:11 +10:00
2019-06-14 11:44:24 +02:00
2019-06-18 22:56:31 -03:00
2019-05-28 08:59:11 +10:00
2019-05-27 18:07:03 +02:00
2019-06-19 12:07:29 +02:00
2019-05-27 18:07:03 +02:00
2019-05-27 18:07:03 +02:00
2019-05-27 18:07:03 +02:00
2019-05-27 18:07:03 +02:00
2019-05-27 18:07:03 +02:00
2019-05-27 18:07:03 +02:00
2019-05-27 18:07:03 +02:00
2019-05-27 18:07:03 +02:00
2019-06-19 12:07:29 +02:00
2019-06-19 12:07:29 +02:00
2019-05-27 18:07:03 +02:00
2019-05-27 18:07:03 +02:00
2019-05-27 18:07:03 +02:00
2019-05-27 18:07:03 +02:00
2019-06-19 12:07:29 +02:00
2019-05-27 18:07:03 +02:00
2019-05-27 18:07:03 +02:00
2019-05-27 18:07:03 +02:00
2019-05-27 18:07:03 +02:00
2019-05-27 18:07:03 +02:00
2019-05-27 18:07:03 +02:00
2019-06-19 12:07:29 +02:00
2019-05-27 18:07:03 +02:00
2019-05-27 18:07:03 +02:00
2019-06-19 12:07:29 +02:00
2019-05-27 18:07:03 +02:00
2019-06-19 12:07:29 +02:00