36c5dde5fd
Phy driver already knows the source PLL id basing on the set usecase and the current PLL id. Stop passing it to the phy_enable call. As a reminder, dsi manager will always use DSI 0 as a clock master in a slave mode, so PLL 0 is always a clocksource for DSI 0 and it is always a clocksource for DSI 1 too unless DSI 1 is used in the standalone mode. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Stephen Boyd <swboyd@chromium.org> # on sc7180 lazor Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Link: https://lore.kernel.org/r/20210331105735.3690009-25-dmitry.baryshkov@linaro.org Signed-off-by: Rob Clark <robdclark@chromium.org>
120 lines
3.2 KiB
C
120 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*/
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#ifndef __DSI_PHY_H__
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#define __DSI_PHY_H__
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/regulator/consumer.h>
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#include "dsi.h"
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#define dsi_phy_read(offset) msm_readl((offset))
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#define dsi_phy_write(offset, data) msm_writel((data), (offset))
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#define dsi_phy_write_udelay(offset, data, delay_us) { msm_writel((data), (offset)); udelay(delay_us); }
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#define dsi_phy_write_ndelay(offset, data, delay_ns) { msm_writel((data), (offset)); ndelay(delay_ns); }
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struct msm_dsi_phy_ops {
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int (*pll_init)(struct msm_dsi_phy *phy);
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int (*enable)(struct msm_dsi_phy *phy,
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struct msm_dsi_phy_clk_request *clk_req);
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void (*disable)(struct msm_dsi_phy *phy);
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void (*save_pll_state)(struct msm_dsi_phy *phy);
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int (*restore_pll_state)(struct msm_dsi_phy *phy);
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};
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struct msm_dsi_phy_cfg {
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struct dsi_reg_config reg_cfg;
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struct msm_dsi_phy_ops ops;
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unsigned long min_pll_rate;
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unsigned long max_pll_rate;
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const resource_size_t io_start[DSI_MAX];
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const int num_dsi_phy;
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const int quirks;
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bool has_phy_regulator;
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bool has_phy_lane;
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};
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extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs;
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struct msm_dsi_dphy_timing {
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u32 clk_zero;
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u32 clk_trail;
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u32 clk_prepare;
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u32 hs_exit;
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u32 hs_zero;
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u32 hs_prepare;
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u32 hs_trail;
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u32 hs_rqst;
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u32 ta_go;
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u32 ta_sure;
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u32 ta_get;
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struct msm_dsi_phy_shared_timings shared_timings;
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/* For PHY v2 only */
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u32 hs_rqst_ckln;
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u32 hs_prep_dly;
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u32 hs_prep_dly_ckln;
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u8 hs_halfbyte_en;
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u8 hs_halfbyte_en_ckln;
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};
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#define DSI_BYTE_PLL_CLK 0
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#define DSI_PIXEL_PLL_CLK 1
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#define NUM_PROVIDED_CLKS 2
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struct msm_dsi_phy {
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struct platform_device *pdev;
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void __iomem *base;
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void __iomem *pll_base;
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void __iomem *reg_base;
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void __iomem *lane_base;
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int id;
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struct clk *ahb_clk;
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struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
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struct msm_dsi_dphy_timing timing;
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const struct msm_dsi_phy_cfg *cfg;
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enum msm_dsi_phy_usecase usecase;
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bool regulator_ldo_mode;
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struct clk_hw *vco_hw;
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bool pll_on;
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struct clk_hw_onecell_data *provided_clocks;
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bool state_saved;
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};
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/*
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* PHY internal functions
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*/
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int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing,
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struct msm_dsi_phy_clk_request *clk_req);
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int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing,
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struct msm_dsi_phy_clk_request *clk_req);
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int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing,
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struct msm_dsi_phy_clk_request *clk_req);
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int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
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struct msm_dsi_phy_clk_request *clk_req);
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#endif /* __DSI_PHY_H__ */
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